MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 152
![IC MPU 66MHZ COLDFIRE 196-MAPBGA](/photos/13/93/139389/mcf5272vm66_sml.jpg)
MCF5272VM66
Manufacturer Part Number
MCF5272VM66
Description
IC MPU 66MHZ COLDFIRE 196-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272VM66
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Cpu Speed
66MHz
Embedded Interface Type
UART, QSPI, USB, TDM
Digital Ic Case Style
BGA
No. Of Pins
196
Supply Voltage Range
3V To 3.6V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Compliant
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Debug Support
5.6.1
Breakpoint hardware can be configured to respond to triggers in several ways. The response desired is
programmed into TDR. As shown in
(CSR[BSTAT]) is provided on the DDATA output port when it is not displaying captured processor status,
operands, or branch addresses.
The breakpoint status is also posted in CSR. Note that CSR[BSTAT] is cleared by a CSR read when either
a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and a level-2 breakpoint is not enabled.
Status is also cleared by writing to TDR.
BDM instructions use the appropriate registers to load and configure breakpoints. As the system operates,
a breakpoint trigger generates the response defined in TDR.
PC breakpoints are treated in a precise manner—exception recognition and processing are initiated before
the excepting instruction is executed. All other breakpoint events are recognized on the processor’s local
bus, but are made pending to the processor and sampled like other interrupt conditions. As a result, these
interrupts are imprecise.
In systems that tolerate the processor being halted, a BDM-entry can be used. With TDR[TRC] = 01, a
breakpoint trigger causes the core to halt (PST = 0xF).
If the processor core cannot be halted, the debug interrupt can be used. With this configuration,
TDR[TRC] = 10, the breakpoint trigger becomes a debug interrupt to the processor, which is treated higher
than the nonmaskable level-7 interrupt request. As with all interrupts, it is made pending until the
processor reaches a sample point, which occurs once per instruction. Again, the hardware forces the PC
breakpoint to occur before the targeted instruction executes. This is possible because the PC breakpoint is
enabled when interrupt sampling occurs. For address and data breakpoints, reporting is considered
imprecise because several instructions may execute after the triggering address or data is detected.
As soon as the debug interrupt is recognized, the processor aborts execution and initiates exception
processing. This event is signaled externally by the assertion of a unique PST value (PST = 0xD) for
multiple cycles. The core enters emulator mode when exception processing begins. After the standard
8-byte exception stack is created, the processor fetches a unique exception vector, 12, from the vector
table.
5-34
Theory of Operation
1
Encodings not shown are reserved for future use.
MCF5272 ColdFire
DDATA[3:0]/CSR[BSTAT]
Table 5-21. DDATA[3:0]/CSR[BSTAT] Breakpoint Response
0000/0000
0010/0001
0100/0010
1010/0101
1100/0110
Table
®
Integrated Microprocessor User’s Manual, Rev. 3
5-21, when a breakpoint is triggered, an indication
1
No breakpoints enabled
Waiting for level-1 breakpoint
Level-1 breakpoint triggered
Waiting for level-2 breakpoint
Level-2 breakpoint triggered
Breakpoint Status
Freescale Semiconductor
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