MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 481

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

21.5
The MCF5272 IEEE 1149.1 implementation includes the three mandatory public instructions (EXTEST,
SAMPLE/PRELOAD, and BYPASS), the optional public ID instruction, plus two additional public
instructions (CLAMP and HI-Z) defined by IEEE 1149.1. The MCF5272 includes a 4-bit instruction
register without parity, consisting of a shift register with four parallel outputs. Data is transferred from the
shift register to the parallel outputs during the update-IR controller state. The 4 bits are used to decode the
instructions in
The parallel output of the instruction register is reset to 0001 in the test-logic-reset controller state. Note
that this preset state is equivalent to the ID instruction.
Freescale Semiconductor
B[3:0]
0000
0001
0010
1001
1100
1101
1111
Instruction
PRELOAD
Instruction Register
SAMPLE/
Reserved
EXTEST
BYPASS
CLAMP
HI-Z
ID
Table
21-2.
The external test (EXTEST) instruction selects the boundary scan register. EXTEST asserts internal
reset for the MCF5272 system logic to force a predictable benign internal state while performing
external boundary scan operations.
By using the TAP, the register is capable of a) scanning user-defined values into the output buffers, b)
capturing values presented to input pins, c) controlling the direction of bidirectional pins, and d)
controlling the output drive of three-state output pins. For more details on the function and uses of
EXTEST, please refer to the IEEE 1149.1 document.
During the capture-IR controller state, the parallel inputs to the instruction shift register are loaded with
the 4-bit binary value (0001). The parallel outputs, however, remain unchanged by this action since an
update-IR signal is required to modify them.
The SAMPLE/PRELOAD instruction selects the boundary scan register and provides two separate
functions. First, it provides a means to obtain a snapshot of system data and control signals. The
snapshot occurs on the rising edge of TCK in the capture-DR controller state. The data can be
observed by shifting it transparently through the boundary scan register.
Because there is no internal synchronization between the IEEE 1149.1 clock (TCK) and the system
clock (CLKOUT), the user must provide some form of external synchronization to achieve meaningful
results.
The second function of SAMPLE/PRELOAD is to initialize the boundary scan register output bits prior
to selection of EXTEST. This initialization ensures that known data appears on the outputs when
entering the EXTEST instruction.
The HI-Z instruction anticipates the need to backdrive the output pins and protect the input pins from
random toggling during circuit board testing. The HIGHZ instruction selects the bypass register, forcing
all output and bidirectional pins to the high-impedance state.
The HI-Z instruction goes active on the falling edge of TCK in the update-IR state when the data held
in the instruction shift register is equivalent to octal 5.
When the CLAMP instruction is invoked, the boundary scan multiplexer control signal EXTEST is
asserted, and the BYPASS register is selected. CLAMP should be invoked after valid data has been
shifted into the boundary scan register, e.g., by SAMPLE/PRELOAD. CLAMP allows static levels to be
presented at the MCF5272 output and bidirectional pins, like EXTEST, but without the shift latency of
the boundary scan register from TDI to TDO.
The BYPASS instruction selects the single-bit bypass register as shown in
shift register path from TDI to the bypass register and, finally, to TDO, circumventing the boundary
scan register. This instruction is used to enhance test efficiency when a component other than the
MCF5272 becomes the device under test. When the bypass register is selected by the current
instruction, the shift register stage is set to a logic zero on the rising edge of TCK in the capture-DR
controller state. Therefore, the first bit to be shifted out after selecting the bypass register is always a
logic zero.
Reserved
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
Table 21-2. Instructions
Description
IEEE 1149.1 Test Access Port (JTAG)
Figure
21-8. This creates a
21-7