MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 318

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Physical Layer Interface Controller (PLIC)
13.5.10 Periodic Status Registers (P0PSR–P3PSR)
All bits in these registers are read only and are set on hardware or software reset.
PnPSR are 16-bit registers containing the interrupt status information for the B- and D-channel transmit
and receive registers for each of the four ports on the MCF5272.
13-22
15–12
P0PSR–3
Bits
10
11
9
8
7
6
5
4
3
Reset
Addr
R/W
15
B2ROE
B1ROE
B2TUE
B1TUE
B2TDE
B1TDE
DROE
Name
DTUE
DTDE
—
—
12
DTUE B2TUE B1TUE DROE B2ROE B1ROE DTDE B2TDE B1TDE DRDF B2RDE B1RDF
Reserved, should be cleared.
D data transmit underrun error. This bit is set when the data in the PLTD transmit data register for the
respective port was transferred to the transmit shadow register, which was already empty indicated by
DTDE. DTUE is automatically cleared, when the PnPSR register has been read by the CPU.
B2 data transmit underrun error. This bit is set when the data in the PnB2TR transmit data register for
the respective port was transferred to the transmit shadow register, which was already empty indicated
by B2TDE. B2TUE is automatically cleared when the PnPSR register has been read by the CPU.
B1 data transmit underrun error. This bit is set when the data in the PnB1TR transmit data register for
the respective port was transferred to the transmit shadow register, which was already empty indicated
by B1TDE. B1TUE is automatically cleared when the PnPSR register has been read by the CPU.
D-Channel data receive overrun error. This bit is set when the data in the D receive shadow register
for the respective port has been transferred to the receive data register PnDRR, which was already full
indicated by DRDF. DROE is automatically cleared when the PnPSR register has been read by the
CPU.
B2 data receive overrun error. This bit is set when the data in the B2 receive shadow register for the
respective port has been transferred to the receive data register PnB2RR, which was already full
indicated by B2RDF. B2ROE is automatically cleared when the PnPSR register has been read by the
CPU.
B1 data receive overrun error. This bit is set when the data in the B1 receive shadow register for the
respective port has been transferred to the receive data register PnB1RR, which was already full
indicated by B1RDF. B1ROE is automatically cleared when the PnPSR register has been read by the
CPU. Note: Overrun and Underrun conditions are caused by the B and/or D-channel receive or
transmit data registers not being read or written prior to a 2-KHz super frame arriving.
D data transmit data empty. This bit is set when the data in the PLTD transmit data register for the
respective port has been transferred to the transmit shadow register. This bit is cleared when the CPU
writes data to PLTD.
B2 data transmit data empty. This bit is set when the data in the PnB2TR transmit data register for the
respective port has been transferred to the transmit shadow register. This bit is cleared when the CPU
writes data to PnB2TR.
B1 data transmit data empty. This bit is set when the data in the PnB1TR transmit data register for the
respective port has been transferred to the transmit shadow register. This bit is cleared when the CPU
writes data to PnB1TR.
MCF5272 ColdFire
11
Figure 13-22. Periodic Status Registers (P0PSR–P3PSR)
MBAR + 0x384 (P0PSR); 0x386 (P1PSR); 0x388 (P2PSR); 0x38A (P3PSR)
10
Table 13-5. P0PSR–P3PSR Field Descriptions
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