MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 466

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Bus Operation
All bursts to and from SRAM or from ROM appear as a sequence of four single longword accesses in the
case of 32-bit wide memory. In the case of 16-bit wide SRAM or ROM memory, a burst appears as a
sequence of eight single word accesses. In the case of 8 bit wide SRAM or ROM memory a burst appears
as a sequence of sixteen single byte accesses. It is never necessary to set CSORn[EXTBURST] when
CSORn[EBI] = 00 or 11. CSBRn[BW] = 11 is invalid for SRAM/ROM; it should be programmed with the
port size.
20.8
All MCF5272 data formats can be located in memory on any byte boundary. A byte operand is properly
aligned at any address; a word operand is misaligned at an odd address; and a longword is misaligned at
an address that is not evenly divisible by four. However, because operands can reside at any byte boundary,
they can be misaligned.
Although the MCF5272 does not enforce any alignment restrictions for data operands (including program
counter (PC) relative data addressing), significant performance degradation can occur when additional bus
cycles are required for longword or word operands that are misaligned. For maximum performance, data
items should be aligned on their natural boundaries. All instruction words and extension words must reside
on word boundaries. An address error exception occurs with any attempt to prefetch an instruction word
at an odd address.
The MCF5272 converts misaligned operand accesses to a sequence of aligned accesses.
illustrates the transfer of a longword operand from a byte address to a 32-bit port, requiring more than one
bus cycle.
word-sized and the transfer requires only two bus cycles.
20-18
•
•
for complete details of access times. To enable this type of transfer, CSOR7[EXTBURST] must be
cleared, CSBR7[EBI] must be 01, and CSBR7[BW] must be 11.
Sixteen byte cache line read bursts from 16-bit wide SDRAM with access times of n-1-1-1-1-1-1-1.
CSOR7[EXTBURST] must be set, CSBR7[EBI] must be 01, and CSBR7[BW] must be 10.
Sixteen byte read or write bursts during Ethernet DMA transfers to/from SDRAM with access
times of n-1-1-1 or n-1-1-1-1-1-1-1 depending on 32 or 16 bit SDRAM port width as described in
the previous two paragraphs.
Misaligned Operands
Figure 20-19
Transfer 1
Transfer 2
Transfer 3
Transfer 1
Transfer 2
MCF5272 ColdFire
31
31
Figure 20-18. Example of a Misaligned Longword Transfer
is similar to the example illustrated in
Figure 20-19. Example of a Misaligned Word Transfer
Byte 3
Byte 1
—
—
—
24 23
24 23
®
Integrated Microprocessor User’s Manual, Rev. 3
Byte 0
—
—
—
—
16 15
16 15
Byte 1
—
—
—
—
Figure 20-18
8 7
8 7
Byte 2
Byte 0
—
—
—
except that the operand is
0
0
Freescale Semiconductor
A[2:0]
A[2:0]
001
010
100
001
100
Figure 20-18