MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 291

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

12.4.4.1
The data flow for control, bulk, and interrupt endpoints can be handled the same way for all 3 types of
endpoints. Control, bulk, and interrupt endpoints all support guaranteed data delivery. If the host detects
an error during the read of a packet from an IN endpoint, it requests that the packet be resent from the
device. The USB FIFO mechanism takes care of this without interrupting the CPU. In a similar fashion,
the USB FIFO mechanism keeps a received packet from being read by the user until the control logic
validates the packet for transmission errors.
12.4.4.1.1
The following example demonstrates how to transmit a transfer on an IN endpoint:
12.4.4.1.2
The following example demonstrates how to handle a received transfer on an OUT endpoint:
12.4.4.2
The data flow for isochronous endpoints must be handled differently than the data flow for
non-isochronous endpoints. Data on isochronous endpoints is generally streaming data. Therefore, there
is no concept of transfers and EOT. In addition, isochronous endpoints differ from other endpoint types in
two distinct ways. Isochronous endpoints support packet sizes up to 1023 bytes and isochronous packets
are never resent. In order to support the large packet sizes, the FIFO size can be less than two times the
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1. Wait until the last transfer is complete (an EOT interrupt has occurred).
2. Write data to the FIFO to fill it.
3. Wait for EOP interrupt or poll EOP bit.
4. Read EPnDP to determine the number of bytes that can be written to the FIFO. Normally, only one
5. Write data to the FIFO to fill it or until all of the data for the transfer has been written.
6. Repeat steps 5–7 until all of the data for the transfer has been written to the FIFO.
7. Clear EPnCTL[IN_DONE].
8. Wait for the EOT interrupt or poll the EOT bit. The user can now begin processing the next transfer.
1. Wait for the EOP interrupt or poll the EOP bit.
2. Read EPnDP to determine number of bytes in the FIFO.
3. Read the indicated number of bytes of data from the FIFO into a buffer.
4. Repeat steps 1–3 until EOT is set.
5. When EOT is set, the transfer is complete. While EOT is set, the FIFO is locked and any packets
6. Read EPnDP to determine the number of bytes in the FIFO if any for the last transfer. The EOT bit
7. Read the indicated number of bytes of data from the FIFO into a buffer.
8. The user can now process the received transfer.
packet should be written unless the software does not service the EOP immediately.
sent for the next transfer cause a NAK response.
can be cleared once this register has been read.
Control, Bulk, and Interrupt Endpoints
Isochronous Endpoints
IN Endpoints
OUT Endpoints
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
Universal Serial Bus (USB)
12-33