MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 359

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

15.3.5
TERs are used to report events recognized by the timer. On recognition of an event, the timer sets the
appropriate TERn bit, regardless of the corresponding interrupt enable bits (ORI and CE) in the TMRn.
Writing a 1 to a bit clears it; writing 0 has no effect. Both bits must be cleared before the timer can negate
the request to the interrupt controller. Both bits may be cleared simultaneously.
Table 15-2
Freescale Semiconductor
15–2
Bits
1
0
Reset
Field
Addr
R/W
Name
CAP
REF
—
describes TERn fields.
15
Timer Event Registers (TER0–TER3)
Reserved, should be cleared.
Output reference event.
0 The counter has not reached the TRR value
1 The counter reached the TRR value. TMR[ORI] is used to enable the interrupt request caused by this
Capture event.
0 The counter value has not been latched into the TCAP.
1 The counter value is latched in the TCAP. TMR[CE] is used to enable capture and the interrupt request
event. Write a 1 to this bit to clear the event condition.
caused by this event. Write a 1 to this bit to clear the event condition.
MCF5272 ColdFire
MBAR + 0x210 (TER0); 0x230 (TER1); 0x250 (TER2); 0x270 (TER3)
Figure 15-6. Timer Event Registers (TER0–TER3)
Table 15-2. TERn Field Descriptions
®
Integrated Microprocessor User’s Manual, Rev. 3
0000_0000_0000_0000
—
Read/Write
Description
2
REF CAP
1
Timer Module
0
15-5