MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 302

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Physical Layer Interface Controller (PLIC)
13.2.3.2
When the incoming B channels contain HDLC encoded data they are presented on the physical line least
significant bit (lsb) first. The Soft HDLC expects the first bit received to be aligned in the lsb position of
a byte, with the last bit received aligned in the msb position.
Because the presentation of HDLC encoded data on the physical interface is lsb (least significant bit) first
for B1 and B2 the lsb is right-aligned in the transmit and receive shift register, that is, the first bit of the
B-channel received is aligned in the lsb position through to the last received bit of a byte that is aligned in
the msb position.
The ordering of the bytes over four frames within the longword register is as for unencoded data; that is,
the first frame is aligned in the MSB through to the fourth frame, which is aligned in the LSB position. See
Figure
13.2.3.3
When the incoming D channels contain HDLC-encoded data, they are presented on the physical line lsb
first. The Soft HDLC expects the first bit received to be aligned in the lsb position of a byte, with the last
bit received aligned in the msb position.
13-6
.
Unencoded
32-bit B1/B2 Receive/Transmit Registers, PnB1RR, PnB2RR, PnB1TR, PnB2TR
HDLC
Encoded
Din/Dout
Din/Dout
13-6.
B
7
DCL
FSR
B
6
B-Channel HDLC Encoded Data
D-Channel HDLC Encoded Data
B
5
Frame 0
B
4
B
B
B
3
7
0
MCF5272 ColdFire
B
Figure 13-6. B-Channel Unencoded and HDLC Encoded Data
B
B
2
6
1
B
B
B
1
5
2
B
B
B
4
3
0
B 1
B
B
B
3
4
7
B
B
B
2
5
6
B
B
B
1
6
5
®
Frame 1
B
B
B
Integrated Microprocessor User’s Manual, Rev. 3
0
7
Frame 0
4
B
B
B
7
0
3
B
B
6
1
B
2
B
B
2
5
B
B
B
1
4
3
B 2
B
B
B
0
4
3
B
B
B
7
2
5
B
B
B
6
6
1
B
B
B
5
7
0
Frame 2
D
D
B
0
0
4
D
D
D
B
1
1
3
B
2
B
1
B
0
B
7
B
6
B
Frame 3
5
Freescale Semiconductor
B
B
7
0
B
4
B
B
6
1
Frame 1
B
B
B
3
5
2
B
B
B
2
4
3
B
B
B
1
3
4
B
B
B
0
2
5