MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 93

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

2.7.5
Table 2-16
Table 2-17
2.8
Exception processing for ColdFire processors is streamlined for performance. Differences from previous
M68000 family processors include the following:
ColdFire processors use an instruction restart exception model but require more software support to
recover from certain access errors. See
Exception processing can be defined as the time from the detection of the fault condition until the fetch of
the first handler instruction has been initiated. It is comprised of the following four major steps:
Freescale Semiconductor
Opcode
jmp
bra
bsr
rte
jsr
rts
•
•
•
•
1. The processor makes an internal copy of the SR and then enters supervisor mode by setting SR[S]
2. The processor determines the exception vector number. For all faults except interrupts, the
A simplified exception vector table
Reduced relocation capabilities using the vector base register
A single exception stack frame format
Use of a single, self-aligning system stack pointer
and disabling trace mode by clearing SR[T]. The occurrence of an interrupt exception also forces
SR[M] to be cleared and the interrupt priority mask to be set to the level of the current interrupt
request.
processor performs this calculation based on the exception type. For interrupts, the processor
performs an interrupt-acknowledge (IACK) bus cycle to obtain the vector number from a
peripheral device. The IACK cycle is mapped to a special acknowledge address space with the
interrupt level encoded in the address.
Opcode
Exception Processing Overview
bcc
shows general branch instruction timing.
shows timing for Bcc instructions.
<ea>
<ea>
<ea>
Branch Instruction Execution Times
Forward Taken
Rn
—
—
—
—
—
—
MCF5272 ColdFire
3(0/0)
Table 2-16. General Branch Instruction Execution Times
3(0/0)
3(0/1)
(An)
Table 2-17. Bcc Instruction Execution Times
—
—
—
—
Forward Not Taken
®
10(2/0)
Table 2-18
5(1/0)
(An)+
Integrated Microprocessor User’s Manual, Rev. 3
—
—
—
—
1(0/0)
–(An)
for details.
—
—
—
—
—
—
Effective Address
Backward Taken
(d16,An)
2(0/1)
3(0/1)
3(0/0)
3(0/1)
—
—
2(0/0)
(d8,An,Xi*SF)
4(0/0)
4(0/1)
—
—
—
—
Backward Not Taken
3(0/0)
(xxx).wl
3(0/0)
3(0/1)
—
—
—
—
ColdFire Core
#<xxx>
—
—
—
—
—
—
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