MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 490
![IC MPU 66MHZ COLDFIRE 196-MAPBGA](/photos/13/93/139389/mcf5272vm66_sml.jpg)
MCF5272VM66
Manufacturer Part Number
MCF5272VM66
Description
IC MPU 66MHZ COLDFIRE 196-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272VM66
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Cpu Speed
66MHz
Embedded Interface Type
UART, QSPI, USB, TDM
Digital Ic Case Style
BGA
No. Of Pins
196
Supply Voltage Range
3V To 3.6V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Compliant
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Electrical Characteristics
23.3.2
Table 23-7
1
2
23-6
B1a
B1b
B1c
B1d
B1e
B1f
B2d
B2e
B2f
B3
B4
B5
Name
All timing references to SDCLK are given to its rising edge when bit 3 of the SDRAM control register is 0.
RSTI, TA, TEA, and INTx are synchronized internally. The setup time must be met only if recognition is needed on a particular
clock edge.
2
2
2
2
2
RSTI valid to SDCLK (setup)
TA valid to SDCLK (setup)
TEA valid to SDCLK (setup)
INTx valid to SDCLK (setup)
BKPT valid to PSTCLK (setup)
Mode selects (BUSW[1:0], WSEL, HiZ) valid to SDCLK (setup) (when RSTI asserted)
SDCLK to asynchronous control inputs (RSTI, TA, TEA, INTx) invalid (hold)
SDCLK to mode selects (BUSW[1,0], WSEL, HIZ) invalid (hold) (when RSTI asserted)
PSTCLK to asynchronous control input BKPT invalid (hold)
RSTI width low
Data input (D[31:0]) valid to SDCLK (setup)
SDCLK to data input (D[31:0]) invalid (hold)
lists processor bus input timings.
Processor Bus Input Timing Specifications
All processor bus timings are synchronous; that is, input setup/hold and
output delay with respect to the rising edge of a reference clock. The
reference clock is the SDCLK output.
All other timing relationships can be derived from these values.
MCF5272 ColdFire
Table 23-7. Processor Bus Input Timing Specifications
®
Integrated Microprocessor User’s Manual, Rev. 3
Characteristic
Control Inputs
Data Inputs
NOTE
1
Freescale Semiconductor
Min
10T
0–66 MHz
6.5
10
14
8
8
8
8
2
2
0
0
Max
—
—
—
—
—
—
—
—
—
—
—
—
Unit
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
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