MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 241
![IC MPU 66MHZ COLDFIRE 196-MAPBGA](/photos/13/93/139389/mcf5272vm66_sml.jpg)
MCF5272VM66
Manufacturer Part Number
MCF5272VM66
Description
IC MPU 66MHZ COLDFIRE 196-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272VM66
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Cpu Speed
66MHz
Embedded Interface Type
UART, QSPI, USB, TDM
Digital Ic Case Style
BGA
No. Of Pins
196
Supply Voltage Range
3V To 3.6V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Compliant
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11.5.13 Receive Control Register (RCR)
The RCR register,
Table 11-20
Freescale Semiconductor
31–4
Bits
Reset
Reset
3
2
1
0
Field
Field
Addr
R/W
R/W
31
15
describes the RCR fields.
MII_MODE
PROM
Name
LOOP
DRT
Figure
—
MCF5272 ColdFire
11-17, controls the operational mode of the receive block.
Reserved, should be cleared.
Promiscuous mode. All frames are accepted regardless of address matching.
MII mode enable. Selects the external interface mode. Setting this bit to one selects MII
mode, setting this bit equal to zero selects seven-wire mode (used only for serial 10 Mbps).
This bit controls the interface mode for both transmit and receive blocks.
Disable receive on transmit
0 Receive path operates independently of transmit (use for full duplex or to monitor transmit
activity in half-duplex mode).
1 Disable reception of frames while transmitting (normally used for half-duplex mode).
Internal loopback. If set, transmitted frames are looped back internal to the FEC and the
transmit output signals are not asserted. The system clock is substituted for the E_TxCLK
when LOOP is asserted. DRT must be set to zero when asserting LOOP.
Figure 11-17. Receive Control Register (RCR)
Table 11-20. RCR Field Descriptions
®
Integrated Microprocessor User’s Manual, Rev. 3
—
0000_0000_0000_0000
0000_0000_0000_0000
MBAR + 0x944
Read/Write
Read/Write
—
Description
4
PROM MII_MODE DRT LOOP
3
2
1
Ethernet Module
16
0
11-23
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