IAR-KSK-IMX25 Freescale Semiconductor, IAR-KSK-IMX25 Datasheet - Page 35
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IAR-KSK-IMX25
Manufacturer Part Number
IAR-KSK-IMX25
Description
KIT DEVELOPMENT I.MX257, ARM926
Manufacturer
Freescale Semiconductor
Series
i.MX25r
Type
MCUr
Datasheets
1.MCIMX25WPDKJ.pdf
(2 pages)
2.IAR-KSK-IMX25.pdf
(154 pages)
3.IAR-KSK-IMX25.pdf
(2 pages)
4.IAR-KSK-IMX25.pdf
(57 pages)
Specifications of IAR-KSK-IMX25
Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
I.MX257
Processor Series
i.MX25
Data Bus Width
16 bit
Interface Type
UART, JTAG, USB, Ethernet, SD/MMC
Core
ARM926EJ-S
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
ARM9
Silicon Core Number
I.MX2
Silicon Family Name
I.MX25
Mcu Supported Families
I.MX25
For Use With/related Products
i.MX25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Note:
1. Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 1.65 V, and 105 °C. Minimum condition for tpr, tpo, and tpv:
2. Minimum condition for tps: wcs model, 1.1 V, I/O 1.65 V, and 105 °C. tps is measured between VIL to VIH for rising edge and
3. Maximum condition for tdit: bcs model, 1.3 V, I/O 1.95 V, and –40 °C.
4. Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 1.65 V and 105 °C. Minimum condition for tpi and trfi: bcs model, 1.3 V,
Table 25
Freescale Semiconductor
Duty cycle
Clock frequency
Output pad transition times (max. drive)
Output pad transition times (high drive)
Output pad transition times (standard drive)
Output pad propagation delay (max. drive),
50%–50% input signals and crossing of
output signals
Output pad propagation delay (high drive),
50%–50% input signals and crossing of
output signals
Output pad propagation delay (standard
drive), 50%–50% input signals and crossing
of output signals
Output pad propagation delay (max. drive),
40%–60% input signals and crossing of
output signals
Output pad propagation delay (high drive),
40%–60% input signals and crossing of
output signals
Output pad propagation delay (standard
drive), 40%–60% input signals and crossing
of output signals
Output enable to output valid delay (max.
drive), 50%–50%
Output enable to output valid delay (high
drive), 50%–50%
Output enable to output valid delay
(standard drive), 50%–50%
bcs model, 1.3 V, I/O 1.95 V and –40 °C. Input transition time from core is 1 ns (20%–80%).
between VIH to VIL for falling edge.
I/O 1.95 V and –40 °C. Input transition time from pad is 5 ns (20%–80%).
shows the AC parameters for mobile DDR pbijtov18_33_ddr_clk I/O.
Parameter
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
Table 25. AC Parameters for Mobile DDR pbijtov18_33_ddr_clk I/O
Symbol
Fduty
tpo
tpo
tpo
tpo
tpo
tpo
tpv
tpv
tpv
tpr
tpr
tpr
f
Condition
25 pF
50 pF
25 pF
50 pF
25 pF
50 pF
15 pF
35 pF
15 pF
35 pF
15 pF
35 pF
15 pF
35 pF
15 pF
35 pF
15 pF
35 pF
15 pF
35 pF
15 pF
35 pF
15 pF
35 pF
Load
—
—
Rise/Fall
0.52/0.51
0.98/0.96
1.13/1.10
2.15/2.10
2.26/2.19
4.30/4.18
1.28/1.19
1.56/1.47
1.54/1.43
2.14/2.04
2.05/1.94
3.27/3.16
1.45/1.36
1.73/1.64
1.70/1.60
2.31/2.21
2.22/2.11
3.43/3.32
1.16/1.12
1.42/1.41
1.39/1.39
1.98/2.02
1.90/1.94
3.07/3.20
Min.
40
—
0.79/0.72
1.49/1.34
1.74/1.55
3.28/2.92
3.46/3.07
6.59/5.79
1.97/1.83
2.37/2.23
2.34/2.20
3.22/3.08
3.11/2.96
4.86/4.72
2.13/2.00
2.53/2.40
2.51/2.37
3.38/3.24
3.27/3.13
5.02/4.88
1.91/1.81
2.31/2.20
2.28/2.18
3.18/3.04
3.09/2.94
4.88/4.66
Typ.
50
—
10.13/8.55
1.25/1.09
2.31/1.98
2.71/2.30
5.11/4.31
5.39/4.56
2.98/2.78
3.57/3.37
3.54/3.33
4.85/4.65
4.70/4.50
7.33/7.12
3.14/2.94
3.74/3.54
3.70/3.50
5.02/4.82
4.87/4.66
7.49/7.29
3.10/2.89
3.72/3.47
3.69/3.43
5.08/4.69
4.95/4.55
7.73/7.05
Rise/Fall
Max.
133
60
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
Notes
—
1
1
1
1
1
35