IAR-KSK-IMX25 Freescale Semiconductor, IAR-KSK-IMX25 Datasheet - Page 79

• Manufacturer Part Number: IAR-KSK-IMX25
• Description: KIT DEVELOPMENT I.MX257, ARM926
• Manufacturer: Freescale Semiconductor
• Series: i.MX25r
• Type: MCUr

Specifications of IAR-KSK-IMX25

• Contents: Board, Cables, CD, Debugger, Power Supply
• Processor To Be Evaluated: I.MX257
• Processor Series: i.MX25
• Data Bus Width: 16 bit
• Interface Type: UART, JTAG, USB, Ethernet, SD/MMC
• Core: ARM926EJ-S
• Silicon Manufacturer: Freescale
• Core Architecture: ARM
• Core Sub-architecture: ARM9
• Silicon Core Number: I.MX2
• Silicon Family Name: I.MX25
• Mcu Supported Families: I.MX25
• For Use With/related Products: i.MX25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Note: All configuration parameters (CSA,CSN,WBEA,WBEN,LBA,LBN,OEN,OEA,RBEA & RBEN) are in cycle units.
Freescale Semiconductor
Ref No.
WE40A
WE41A
(muxed
(muxed
WE41
WE42
WE43
WE44
WE45
WE46
WE47
WE48
For the value of parameters WE4–WE21, see column BCD = 0 in
CS Assertion. This bit field determines when the CS signal is asserted during read/write cycles.
CS Negation. This bit field determines when the CS signal is negated during read/write cycles.
BE Assertion. This bit field determines when the BE signal is asserted during read cycles.
BE Negation. This bit field determines when the BE signal is negated during read cycles.
Output maximum delay from internal driving ADDR/control FFs to chip outputs.
Output maximum delay from CS[x] internal driving FFs to CS[x] out.
DATA maximum delay from chip input data to its internal FF.
A/D)
A/D)
DTACK maximum delay from chip dtack input to its internal FF.
Table 57. WEIM Asynchronous Timing Parameters Relative to Chip Select Table (continued)
CS[x] Valid to Output Data Valid
CS[x] Valid to Output Data Valid
CS[x] Invalid to DTACK invalid
DTACK Valid to CS[x] Invalid
EB[y] Invalid to CS[x] Invalid
Output Data Invalid to CS[x]
CS[x] Valid to LBA Invalid
CS[x] Invalid to Input Data
CS[x] Valid to EB[y] Valid
Input Data Valid to CS[x]
(Write access)
(Write access)
Parameter
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
Invalid
Invalid
invalid
WE14 – WE6 + (LBN + LBA + 1
WE12 – WE6 + (WBEA – CSA)
WE7 – WE13 + (WBEN – CSN)
MAXCO – MAXCSO + MAXDTI
MAXCO – MAXCSO + MAXDI
WLBA + ADH + 1 – WCSA)
Synchronous Measured
WE16 – WE6 + (WLBN +
WE16 – WE6 – WCSA
WE17 – WE7 – CSN
Determination By
Parameters
– CSA)
0
0
1
Table
56.
–3 + (LBN + LBA +
MAXCSO
e:
MAXCSO
MAXCO
MAXCO
1 – CSA)
+ MAXDTI
MAXDI
Min
—
—
—
—
—
0
0
7Note:Not
6
6 –
8
7
–
+
9
3 + (WLBN + WLBA +
3 + (LBN + LBA + 1 –
–3 + (WBEN – CSN)
supported by SoC)
3 + (WBEA – CSA)
ADH + 1 – WCSA)
(If 133 MHz is
3 – WCSA
3 – CSN
CSA)
Max
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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