IAR-KSK-IMX25 Freescale Semiconductor, IAR-KSK-IMX25 Datasheet - Page 88
![KIT DEVELOPMENT I.MX257, ARM926](/photos/37/58/375862/imx25kbsbd_sml.jpg)
IAR-KSK-IMX25
Manufacturer Part Number
IAR-KSK-IMX25
Description
KIT DEVELOPMENT I.MX257, ARM926
Manufacturer
Freescale Semiconductor
Series
i.MX25r
Type
MCUr
Datasheets
1.MCIMX25WPDKJ.pdf
(2 pages)
2.IAR-KSK-IMX25.pdf
(154 pages)
3.IAR-KSK-IMX25.pdf
(2 pages)
4.IAR-KSK-IMX25.pdf
(57 pages)
Specifications of IAR-KSK-IMX25
Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
I.MX257
Processor Series
i.MX25
Data Bus Width
16 bit
Interface Type
UART, JTAG, USB, Ethernet, SD/MMC
Core
ARM926EJ-S
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
ARM9
Silicon Core Number
I.MX2
Silicon Family Name
I.MX25
Mcu Supported Families
I.MX25
For Use With/related Products
i.MX25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MCIMX25WPDKJ PDF datasheet
- IAR-KSK-IMX25 PDF datasheet #2
- IAR-KSK-IMX25 PDF datasheet #3
- IAR-KSK-IMX25 PDF datasheet #4
- Current page: 88 of 154
- Download datasheet (2Mb)
1
3.7.9.2
The MDC frequency is designed to be equal to or less than 2.5 MHz to comply with the IEEE 802.3
standard MII specification. However the FEC can function correctly with a maximum MDC frequency of
15 MHz.
Figure 58
shown in the figure.
88
M10
M11
M12
M13
M14
M15
M9
FEC_COL has the same timing in 10-Mbit 7-wire interface mode.
1
ID
ID
FEC_MDIO (output)
FEC_MDC (output)
FEC_MDIO (input)
FEC_MDC falling edge to FEC_MDIO output invalid (min.
propagation delay)
FEC_MDC falling edge to FEC_MDIO output valid (max.
propagation delay)
FEC_MDIO (input) to FEC_MDC rising edge setup
FEC_MDIO (input) to FEC_MDC rising edge hold
FEC_MDC pulse width high
FEC_MDC pulse width low
FEC_CRS to FEC_COL minimum pulse width
shows MII asynchronous input timings.
MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
Figure 58. MII Serial Management Channel Timing Diagram
Table 64. MII Asynchronous Inputs Signal Timing
Table 65. MII Serial Management Channel Timing
Characteristic
Characteristic
M12
M13
Table 65
M14
describes the timing parameters (M10—M15)
Min.
1.5
Min.
40%
40%
M10
18
—
0
0
M11
M15
Max.
—
Max.
60%
60%
—
—
—
5
FEC_TX_CLK period
Freescale Semiconductor
FEC_MDC period
FEC_MDC period
Unit
Unit
ns
ns
ns
ns
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