IAR-KSK-IMX25 Freescale Semiconductor, IAR-KSK-IMX25 Datasheet - Page 41
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IAR-KSK-IMX25
Manufacturer Part Number
IAR-KSK-IMX25
Description
KIT DEVELOPMENT I.MX257, ARM926
Manufacturer
Freescale Semiconductor
Series
i.MX25r
Type
MCUr
Datasheets
1.MCIMX25WPDKJ.pdf
(2 pages)
2.IAR-KSK-IMX25.pdf
(154 pages)
3.IAR-KSK-IMX25.pdf
(2 pages)
4.IAR-KSK-IMX25.pdf
(57 pages)
Specifications of IAR-KSK-IMX25
Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
I.MX257
Processor Series
i.MX25
Data Bus Width
16 bit
Interface Type
UART, JTAG, USB, Ethernet, SD/MMC
Core
ARM926EJ-S
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
ARM9
Silicon Core Number
I.MX2
Silicon Family Name
I.MX25
Mcu Supported Families
I.MX25
For Use With/related Products
i.MX25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Note:
1. Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 1. V, and 105 °C. Minimum condition for tpr, tpo, and tpv: bcs
2. Minimum condition for tps: wcs model, 1.1 V, I/O 1.7 V, and 105 °C. tps is measured between VIL to VIH for rising edge and
3. Maximum condition for tdit: bcs model, 1.3 V, I/O 1.9 V, and –40 °C.
4. Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 1.7 V and 105 °C. Minimum condition for tpi and trfi: bcs model, 1.3 V,
Table 30
Note:
1. Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 1. V, and 105 °C. Minimum condition for tpr, tpo, and tpv: bcs
Freescale Semiconductor
Duty cycle
Clock frequency
Output pad transition times
Output pad propagation delay, 50%–50%
input signals and crossing of output signals
Output pad propagation delay, 40%–60%
input signals and crossing of output signals
Output enable to output valid delay,
50%–50%
Output enable to output valid delay,
40%–60%
Output pad slew rate
Output pad dI/dt
Input pad transition times
Input pad propagation delay, 50%–50%
Input pad propagation delay, 40%–60%
Output pad dI/dt
Input pad transition times
Input pad propagation delay, 50%–50%
Input pad propagation delay, 40%–60%
model, 1.3 V, I/O 1.9 V and –40 °C. Input transition time from core is 1 ns (20%–80%).
between VIH to VIL for falling edge.
I/O 1.9 V and –40 °C. Input transition time from pad is 5 ns (20%–80%).
model, 1.3 V, I/O 1.9 V and –40 °C. Input transition time from core is 1 ns (20%–80%).
shows AC parameters for DDR2 pbijtov18_33_ddr_clk I/O.
Parameter
Parameter
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
Table 30. AC Parameters for DDR2 pbijtov18_33_ddr_clk I/O
Table 29. AC Parameters for DDR2 I/O (continued)
Symbol
Symbol
Fduty
tpo
tpo
tpv
tpv
tps
tdit
tdit
tpr
trfi
trfi
tpi
tpi
tpi
tpi
f
Condition
Condition
1.0 pF
1.0 pF
1.0 pF
1.0 pF
1.0 pF
1.0 pF
25 pF
25 pF
50 pF
25 pF
50 pF
25 pF
50 pF
25 pF
50 pF
25 pF
50 pF
25 pF
50 pF
50 pF
50 pF
25 pF
Load
Load
—
—
Rise/Fall
0.07/0.08 0.10/0.12 0.17/0.20
0.83/0.99 1.23/1.49 1.79/2.04
1.65/1.81 2.05/2.31 2.60/2.84
0.53/0.52
1.01/0.98
1.47/1.38
1.75/1.67
1.32/1.28
1.66/1.65
1.40/1.37
1.67/1.66
0.86/0.98
0.07/0.08 0.10/0.12
0.89/0.87 1.41/1.37
1.71/1.69 2.22/2.18
Rise/Fall
0.46/054
1.3/1.21
1.59/1.5
Min.
Min.
65
70
40
72
77
—
0.80/0.72
1.49/1.34
1.97/1.84
2.37/2.24
2.13/2.00
2.54/2.40
2.11/2.00
2.61/2.50
2.16/2.06
2.56/2.45
0.72/0.81
1.35/1.5
Typ.
Typ.
157
167
172
183
50
—
Rise/Fall
3.072/2.87
1.19/1.04
2.21/1.90
2.91/2.71
3.48/3.28
3.65/3.45
3.31/3.12
4.06/3.81
3.30/3.13
3.89/3.67
2.15/2.19
1.12/1.16
0.17/0.20
2.16/2.07
2.98/2.88
Rise/Fall
Max.
373
396
Max.
133
400
422
60
mA/ns
Units
mA/ns
Units
ns
ns
ns
MHz
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
%
Notes
Notes
3
4
—
—
1
1
1
1
1
2
3
4
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