A000047 Arduino, A000047 Datasheet - Page 19
A000047
Manufacturer Part Number
A000047
Description
MCU, MPU & DSP Development Tools Mega2560
Manufacturer
Arduino
Series
-r
Type
MCUr
Specifications of A000047
Processor To Be Evaluated
ATmega2560
Interface Type
USB, I2C, SPI
Dimensions
4 in x 2.1 in
Operating Supply Voltage
5 V
Contents
Board
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
ATmega2560
- Current page: 19 of 444
- Download datasheet (10Mb)
2549M–AVR–09/10
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec-
tor in order to execute the interrupt handling routine, and hardware clears the corresponding
Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)
to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt
Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction. The following example shows how this can be used to avoid interrupts during the
timed EEPROM write sequence.
When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-
cuted before any pending interrupts, as shown in this example.
Assembly Code Example
C Code Example
in r16, SREG
cli
sbi EECR, EEMPE
sbi EECR, EEPE
out SREG, r16
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
__disable_interrupt();
EECR |= (1<<EEMPE); /* start EEPROM write */
EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */
; disable interrupts during timed sequence
; store SREG value
; start EEPROM write
; restore SREG value (I-bit)
ATmega640/1280/1281/2560/2561
19
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