LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 126

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Quadrant Primary Clock
Any primary clock may be assigned to a quadrant clock. The clock may be assigned to a single quadrant or to two
adjacent quadrants (not diagonally adjacent).
When a quadrant clock net is used, the user must ensure that the registers each clock drives can be assigned in
that quadrant without any routing issues.
In the Quadrant Primary Clocking scheme, the maximum number of primary clocks is 32, as long as all the primary
clock sources are available.
Figure 9-3. Clock Attributes in the Pre-map Preference Editor
Refer to Appendix A for detailed clock network diagrams.
sysCLOCK™ PLL
The LatticeXP2 PLL provides features such as clock injection delay removal, frequency synthesis, phase/duty
cycle adjustment, and dynamic delay adjustment. Figure 9-4 shows the block diagram of the LatticeXP2 PLL.
Figure 9-4. LatticeXP2 PLL Block Diagram
DPHASE
WRDEL
DDUTY
CLKFB
RSTK
CLKI
RST
Divider
CLKFB
Divider
CLKI
Internal Feedback
Frequency
Phase &
Detector
Controlled
Oscillator/
Voltage
Loop
Filter
9-4
Detect
Lock
CLKOP
Divider
Phase Duty
Duty Trim
Duty Trim
CLKOK
LatticeXP2 sysCLOCK PLL
Divider
Cycle
Design and Usage Guide
÷3
CLKOK2
CLKOS
CLKOP
CLKOK
LOCK