LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 269
LFXP2-5E-5FTN256I
Manufacturer Part Number
LFXP2-5E-5FTN256I
Description
FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-5E-5FTN256I
Number Of Macrocells
5000
Number Of Programmable I/os
172
Data Ram Size
169984
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FTBGA-256
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
169984
Number Of I /o
172
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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end process;
addout <= multout_reg + dataout_reg;
process (clk, reset)
begin
if (reset = ‘1’) then
elsif (clk’event and clk=’1’) then
end if;
end process;
end arch;
The above RTL will infer the following block diagram:
Figure 13-11. MULT18X18MACB Block Diagram
This block diagram can be mapped directly into the sysDSP primitives. Note that if a test point were added between
the multiplier and the accumulator, or two output registers, etc. the code could not be mapped into a
MULT18X18MACB of a sysDSP Block. Therefore, options that could be included in a design are input registers,
pipeline registers, etc. For more Inferring design examples refer to EXAMPLES in the ispLEVER software.
dataout_reg <= (others => ‘0’);
dataout_reg <= addout;
Multiplier
13-10
Accumulator
Lattice XP2 sysDSP Usage Guide
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