LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 151

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

November 2008
Introduction
This technical note discusses memory usage for the LatticeXP2™ device family. It is intended to be used by design
engineers as a guide for integrating the User TAG, EBR- (Embedded Block RAM) and PFU-based memories in this
device family using the ispLEVER
The architecture of these devices provides resources for FPGA on-chip memory applications. The sysMEM™ EBR
complements the distributed PFU-based memory. Single-Port RAM, Dual-Port RAM, Pseudo Dual-Port RAM, FIFO
and ROM memories can be constructed using the EBR. LUTs and PFU can implement Distributed Single-Port
RAM, Dual-Port RAM and ROM. User TAG memories in varying sizes, depending on the specific chip, are also on
the device.
The capabilities of the User TAG memory, EBR RAM and PFU RAM are referred to as primitives and are described
later in this document. Designers can utilize the memory primitives in two ways via the IPexpress™ tool in the isp-
LEVER software. The IPexpress GUI allows users to specify the memory type and size required. IPexpress takes
this specification and constructs a netlist to implement the desired memory by using one or more of the memory
primitives.
The remainder of this document discusses the use of IPexpress, memory modules and memory primitives.
Memories in LatticeXP2 Devices
There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional Unit
without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM and register functions.
The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are opti-
mized for flexibility allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged
in a two-dimensional array. Only one type of block is used per row.
The LatticeXP2 family of devices contains up to two rows of sysMEM EBR blocks. sysMEM EBRs are large, dedi-
cated 18K fast memory blocks. Each sysMEM block can be configured in a variety of depths and widths of RAM or
ROM. Each LatticeXP2 device also contains one dedicated row of User TAG memory with up to 451 bytes of
space.
Table 10-1. LatticeXP2 LUT and Memory Densities
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
EBR Rows
EBR Blocks
EBR Bits
Distributed RAM Bits
Total Memory Bits
Parameter
®
design tool.
165888
176256
XP2-5
10368
1
9
LatticeXP2 Memory Usage Guide
221184
239616
18432
XP2-8
10-1
12
1
XP2-17
276480
311040
34560
15
1
XP2-30
387072
451584
64512
21
1
Technical Note TN1137
XP2-40
884736
967680
tn1137_01.8
82944
48
2