LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 260

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

February 2007
Introduction
This technical note discusses how to access the features of the LatticeXP2™ sysDSP™ (Digital Signal Process-
ing) Block described in the
improvement over traditional LUT-based implementations. Table 13-1 provides an example of the performance and
area benefits of this approach:
Table 13-1. sysDSP Block vs. LUT-based Multipliers
sysDSP Block Hardware
The LatticeXP2 sysDSP Blocks are located in rows throughout device. Below is a block diagram of one of the sys-
DSP Blocks:
Figure 13-1. LatticeXP2 sysDSP Block
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Input Registers from
SRO of left-side
sysDSP Block (or
tied to zero if none)
Intermediate
Pipeline Registers
1. These timing numbers were generated using the ispLEVER
Multiplier Width
version.
Output
Registers
18x18
36x36
9x9
*Can only be routed to general logic routing when configured with less than
three MULT18X18.
Note: Each sysDSP Block spans nine columns of PFUs.
36
Add/Sub (36) (9x9 ≤ 2x18) 1
9x9
PR0 (36)
Mult18-0
LatticeXP2 Family Data
Input, Multiplier, Output
Input, Multiplier, Output
Input, Multiplier, Output
Accumulator (52) 1
In Reg A0
In Reg B0
Register Pipelining
9x9
Summation (38) (Two 20 Bits in 9x9 Mode)
9x9
PR1 (36)
Mult18-1
In Reg A1
In Reg B1
36x36 (Mult36)
9x9
Sheet. Designs targeting the sysDSP Block can offer significant
f
In Reg A2
In Reg B2
Uses One sysDSP Block
MAX
9x9
Add/Sub (36) (9x9 ≤ 2x18) 3
13-1
PR2 (36)
Mult18-2
®
365
365
323
design tool. Exact performance may vary with design and tool
Accumulator (52) 3
(MHz)
9x9
XP2-17-7
1
In Reg A3
In Reg B3
9x9
LUTs
PR3 (36)
Mult18-3
0
0
0
9x9
LatticeXP2 sysDSP
f
36
MAX
103
76
50
(MHz)
Uses LUTs
Usage Guide
XP2-17-7
Adder, Subtractor and
Accumulator Functions
36x36, 18x18 and
9x9 Multiplier Functions
Output Registers to SRI
of right-side sysDSP Block
(if it exists) and/or General
Logic*
Technical Note TN1140
1
LUTs
2732
192
698
tn1140_01.0