LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 281

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Lattice XP2 sysDSP Usage Guide
parameter REG_PIPELINE1_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_PIPELINE1_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_PIPELINE1_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_OUTPUT_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_OUTPUT_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_OUTPUT_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_SIGNEDA_0_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_SIGNEDA_0_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_SIGNEDA_0_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_SIGNEDA_1_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_SIGNEDA_1_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_SIGNEDA_1_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_SIGNEDB_0_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_SIGNEDB_0_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_SIGNEDB_0_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_SIGNEDB_1_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_SIGNEDB_1_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_SIGNEDB_1_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_ADDNSUB_0_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_ADDNSUB_0_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_ADDNSUB_0_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_ADDNSUB_1_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_ADDNSUB_1_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_ADDNSUB_1_RST = “ RST0, RST1, RST2, RST3 “;
parameter GSR = “ Enabled, Disabled “;
MULT9X9ADDSUBSUMB
input A08,A07,A06,A05,A04,A03,A02,A01,A00;
input A18,A17,A16,A15,A14,A13,A12,A11,A10;
input A28,A27,A26,A25,A24,A23,A22,A21,A20;
input A38,A37,A36,A35,A34,A33,A32,A31,A30;
input B08,B07,B06,B05,B04,B03,B02,B01,B00;
input B18,B17,B16,B15,B14,B13,B12,B11,B10;
input B28,B27,B26,B25,B24,B23,B22,B21,B20;
input B38,B37,B36,B35,B34,B33,B32,B31,B30;
input SIGNEDA, SIGNEDB,ADDNSUB1,ADDNSUB3;
input SOURCEA0, SOURCEA1, SOURCEA2, SOURCEA3;
input SOURCEB0, SOURCEB1, SOURCEB2, SOURCEB3;
input CE0,CE1,CE2,CE3,CLK0,CLK1,CLK2,CLK3,RST0,RST1,RST2,RST3;
input SRIA8,SRIA7,SRIA6,SRIA5,SRIA4,SRIA3,SRIA2,SRIA1,SRIA0;
input SRIB8,SRIB7,SRIB6,SRIB5,SRIB4,SRIB3,SRIB2,SRIB1,SRIB0;
output SROA8,SROA7,SROA6,SROA5,SROA4,SROA3,SROA2,SROA1,SROA0;
output SROB8,SROB7,SROB6,SROB5,SROB4,SROB3,SROB2,SROB1,SROB0;
output
SUM19,SUM18,SUM17,SUM16,SUM15,SUM14,SUM13,SUM12,SUM11,SUM10,SUM9,SUM8,SUM7,SUM6,SUM5,SUM4,SUM3,SUM
2,SUM1,SUM0;
parameter REG_INPUTA0_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_INPUTA0_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_INPUTA0_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_INPUTA1_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_INPUTA1_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_INPUTA1_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_INPUTA2_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_INPUTA2_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_INPUTA2_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_INPUTA3_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_INPUTA3_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_INPUTA3_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_INPUTB0_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_INPUTB0_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_INPUTB0_RST = “ RST0, RST1, RST2, RST3 “;
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