LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 182

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 10-33 show the behavior of non-pipelined FIFO_DC or FIFO_DC without output registers. When we pipeline
the registers, the output data is delayed by one clock cycle. There is an extra option for the output registers to be
enabled by the RdEn signal.
Figures 10-34 to 10-37 show the similar waveforms for the FIFO_DC with output register and without output regis-
ter enable with RdEn. Note that flags are asserted and de-asserted with similar timing to the FIFO_DC without out-
put registers. However, it is only the data out 'Q' that is delayed by one clock cycle.
Figure 10-34. FIFO_DC with Output Registers, Start of Data Write Cycle
RPReset
WrClock
RdClock
Almost
Almost
Empty
Empty
Reset
WrEn
RdEn
Data
Full
Full
Q
Invalid Data
Data_1
Data_2
10-32
Invalid Q
Data_3
Data_4
LatticeXP2 Memory Usage Guide
Data_5