LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 3

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
DC and Switching Characteristics
DDR Memory Support...................................................................................................................................... 2-30
sysIO Buffer ..................................................................................................................................................... 2-34
IEEE 1149.1-Compliant Boundary Scan Testability......................................................................................... 2-37
flexiFLASH Device Configuration..................................................................................................................... 2-38
Density Shifting ................................................................................................................................................ 2-41
Absolute Maximum Ratings ............................................................................................................................... 3-1
Recommended Operating Conditions ................................................................................................................ 3-1
On-Chip Flash Memory Specifications............................................................................................................... 3-1
Hot Socketing Specifications.............................................................................................................................. 3-2
DC Electrical Characteristics.............................................................................................................................. 3-2
Supply Current (Standby)................................................................................................................................... 3-3
Initialization Supply Current ............................................................................................................................... 3-4
Programming and Erase Flash Supply Current ................................................................................................. 3-5
sysIO Recommended Operating Conditions...................................................................................................... 3-6
sysIO Single-Ended DC Electrical Characteristics............................................................................................. 3-7
sysIO Differential Electrical Characteristics ....................................................................................................... 3-8
Typical Building Block Function Performance.................................................................................................. 3-14
Derating Timing Tables .................................................................................................................................... 3-15
LatticeXP2 External Switching Characteristics ................................................................................................ 3-16
LatticeXP2 Internal Switching Characteristics.................................................................................................. 3-19
EBR Timing Diagrams...................................................................................................................................... 3-22
LatticeXP2 Family Timing Adders .................................................................................................................... 3-24
sysCLOCK PLL Timing .................................................................................................................................... 3-27
LatticeXP2 sysCONFIG Port Timing Specifications......................................................................................... 3-28
On-Chip Oscillator and Configuration Master Clock Characteristics................................................................ 3-29
Flash Download Time (from On-Chip Flash to SRAM) .................................................................................... 3-30
Flash Program Time......................................................................................................................................... 3-30
Flash Erase Time ............................................................................................................................................. 3-30
FlashBAK Time (from EBR to Flash) ............................................................................................................... 3-31
JTAG Port Timing Specifications ..................................................................................................................... 3-31
Switching Test Conditions................................................................................................................................ 3-33
Control Logic Block ................................................................................................................................. 2-30
DLL Calibrated DQS Delay Block ........................................................................................................... 2-32
Polarity Control Logic .............................................................................................................................. 2-33
DQSXFER............................................................................................................................................... 2-34
sysIO Buffer Banks ................................................................................................................................. 2-34
Typical sysIO I/O Behavior During Power-up.......................................................................................... 2-35
Supported sysIO Standards .................................................................................................................... 2-35
Hot Socketing.......................................................................................................................................... 2-37
Serial TAG Memory................................................................................................................................. 2-39
Live Update Technology ......................................................................................................................... 2-39
Soft Error Detect (SED) Support ............................................................................................................. 2-40
On-Chip Oscillator................................................................................................................................... 2-40
LVDS......................................................................................................................................................... 3-8
Differential HSTL and SSTL...................................................................................................................... 3-8
LVDS25E .................................................................................................................................................. 3-8
LVCMOS33D ............................................................................................................................................ 3-9
BLVDS .................................................................................................................................................... 3-10
LVPECL .................................................................................................................................................. 3-11
RSDS ...................................................................................................................................................... 3-12
MLVDS.................................................................................................................................................... 3-13
Pin-to-Pin Performance (LVCMOS25 12mA Drive) ................................................................................ 3-14
Register-to-Register Performance .......................................................................................................... 3-14
2
LatticeXP2 Family Handbook
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