LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 132

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Duty Cycle Select settings are described in Table 9-6.
Table 9-6. Duty Cycle Select Settings
PLL Usage in IPexpress™
IPexpress is used to create and configure a PLL. The graphical user interface is used to select parameters for the
PLL. The result is an HDL model to be used in the simulation and synthesis flow.
Figure 9-8 shows the main window when PLL is selected. The only entry required in this window is the module
name. Other entries are set to the project settings. Users may change these entries, if desired. After entering the
module name of choice, clicking on Customize will open the Configuration Tab window as shown in Figure 9.
Note: PHASE/DUTY_CTNL is selected in the GUI ‘PLL Phase & Duty Options’ box and if it is set to ‘Dynamic
Mode’, then both DPHASE[3:0] and DDUTY[3:0] inputs must be provided. If one of these inputs is a fixed value,
the inputs must be tied to the desired fixed logic levels.
DDUTY[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
(1/16th of a Period)
Duty Cycle
9-10
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
LatticeXP2 sysCLOCK PLL
Not Supported
Not Supported
Not Supported
Design and Usage Guide
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