LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 268

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Targeting the sysDSP Block by Inference
The Inferencing flow enables the design tools to infer sysDSP Blocks from a HDL design. It is important to note that
when using the Inferencing flow, unless the code style matches the sysDSP Block, results will not be optimal. Con-
sider the following Verilog and VHDL examples:
// This Verilog example will be mapped into single MULT18X18MACB with the output register enabled
module mult_acc (dataout, dataax, dataay, clk);
endmodule
-- This VHDL example will be mapped into single MULT18X18MACB with all the registers enabled
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mac is
port (clk, reset : in std_logic;
end;
architecture arch of mac is
signal dataax_reg, dataay_reg : std_logic_vector(8 downto 0);
signal multout, multout_reg : std_logic_vector(17 downto 0);
signal addout : std_logic_vector(17 downto 0);
signal dataout_reg : std_logic_vector(17 downto 0);
begin
dataout <= dataout_reg;
process (clk, reset)
begin
if (reset = ‘1’) then
elsif (clk’event and clk=’1’) then
end if;
end process;
multout <= dataax_reg * dataay_reg;
process (clk, reset)
begin
if (reset = ‘1’) then
elsif (clk’event and clk=’1’) then
end if;
dataax_reg <= (others => ‘0’);
dataay_reg <= (others => ‘0’);
dataax_reg <= dataax;
dataay_reg <= dataay;
multout_reg <= (others => ‘0’);
multout_reg <= multout;
output [16:0] dataout;
input [7:0] dataax, dataay;
input clk;
reg
wire [15:0] multa = dataax * dataay; // 9x9 Multiplier
wire [16:0] adder_out;
assign adder_out = multa + dataout; // Accumulator
always @(posedge clk)
begin
end
dataout <= adder_out; // Output Register of the Accumulator
dataax, dataay : in std_logic_vector(8 downto 0);
dataout : out std_logic_vector(17 downto 0));
[16:0] dataout;
13-9
Lattice XP2 sysDSP Usage Guide