ISL6534CRZ Intersil, ISL6534CRZ Datasheet

no-image

ISL6534CRZ

Manufacturer Part Number
ISL6534CRZ
Description
IC CTRLR PWM DUAL LINEAR 32QFN
Manufacturer
Intersil
Datasheet

Specifications of ISL6534CRZ

Topology
Step-Down (Buck) Synchronous (2), Linear (LDO) (1)
Function
Any Function
Number Of Outputs
3
Frequency - Switching
300kHz ~ 1MHz
Voltage/current - Output 1
Controller
Voltage/current - Output 2
Controller
Voltage/current - Output 3
Controller
W/led Driver
No
W/supervisor
No
W/sequencer
Yes
Voltage - Supply
3.3 V ~ 12 V
Operating Temperature
0°C ~ 70°C
Mounting Type
*
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISL6534CRZ
Manufacturer:
TI
Quantity:
7 155
Part Number:
ISL6534CRZ
Manufacturer:
ISL
Quantity:
20 000
Part Number:
ISL6534CRZ-T
Manufacturer:
INTERSIL
Quantity:
11 900
Part Number:
ISL6534CRZ-T
Manufacturer:
INTERSIL
Quantity:
20 000
Company:
Part Number:
ISL6534CRZ-T
Quantity:
865
Part Number:
ISL6534CRZR5229
Manufacturer:
Intersil
Quantity:
135
Dual PWM with Linear
The ISL6534 is a versatile triple regulator that has two
independent synchronous-rectified buck controllers with
integrated 12V gate drivers (OUT1 and OUT2) and a linear
controller (OUT3) to offer precision regulation of up to three
voltage rails. An optional shunt regulator allows 12V only
operation, when a 5V supply is not available.
Each controller has independent soft-start and enable
functions combined on a single pin. A capacitor from each
SS/EN pin to ground sets the soft-start time, and pulling
SS/EN below 1.0V disables the controller. The SS/EN pins
can be controlled independently or they can be ganged
together to provide complete control of start-up coordination.
The PGOOD function indicates when all regulators have
completed their soft-start and provides an indication of short-
circuit conditions on either switching regulator.
There are two ways to control the switching frequency of the
PWM regulators. The default switching frequency is 300kHz
(FS_SYNC to ground). A resistor from FS_SYNC to ground
increases the switching frequency (up to 1MHz). Connecting
the gate signal from another PWM IC synchronizes the
ISL6534 switchers to the frequency of the other controller.
This allows independent regulators operating at a common
frequency to avoid low-frequency beats. The gate drivers for
DDR mode can be staggered by 90° in order to minimize
cross-conduction.
Switcher OUT1 has an internal reference for regulating any
voltage down to 0.6V. OUT2 has current sinking capability
and an external reference input allowing convenient
connection to OUT1 through a resistor divider for DDRAM
applications. The 3.3V reference pin provides the option for
independent regulation of OUT2. The linear controller drives
an external N-Channel MOSFET, making the ISL6534 one of
the most versatile regulators available.
Simplified Block Diagram
SS1/EN1
SS2/EN2
SS3/EN3
COMP1
COMP2
REFIN
VREF
FB1
FB2
FB3
LINEAR CONTROLLER
PWM CONTROLLER
PWM CONTROLLER
®
OUT1
OUT2
OUT3
3.3V
1
Data Sheet
BOOT1
UGATE1
LGATE1
BOOT2
UGATE2
LGATE2
REFOUT
PGOOD
FS/SYNC
DRIVE3
1-888-INTERSIL or 1-888-468-3774
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• Two Synchronous-Rectified Buck Controllers
• Switcher References
• Switcher Clocking
• Single Linear Controller
• 12V and 5V Supplies Required (but optional shunt
• Three Independent Soft-Start/Enable Pins
• PGOOD Output Indicates All Outputs Available
• Thermally Enhanced QFN or TSSOP Package
• QFN Package:
• Pb-Free Plus Anneal Available (RoHS Compliant)
November 18, 2005
- Voltage Mode Control
- VIN Range up to 12V
- VOUT Range from 0.6V to 6V
- 12V LGATE Drivers; up to 12V Boot Strap for UGATE
- 0.6V Reference for OUT1
- 3.3V Reference Output for OUT2
- External Reference Input for OUT2
- Buffered VTT Reference Output
- Phase Options for Optimal Clock Relationship
- Resistor-Selectable Switching Frequency (300kHz
- Synchronization-Capable Switching Frequency
- Drives N-Channel MOSFET
- 0.6V Reference
- VIN Range up to 12V
- VOUT Range from 0.6V to 3.3V
regulator can generate VCC = 5.8V from 12V)
- Gang Together or Control Independently
- Compliant to JEDEC PUB95 MO-220
- Near Chip Scale Package footprint, which improves
default; Resistor to Ground for 300kHz to 1MHz range)
(Connect FS_SYNC to Separate Regulator)
QFN - Quad Flat No Leads - Package Outline
PCB efficiency and has a thinner profile
All other trademarks mentioned are the property of their respective owners.
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved
ISL6534
FN9134.2

Related parts for ISL6534CRZ

ISL6534CRZ Summary of contents

Page 1

... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL6534 ...

Page 2

... ISL6534CV ISL6534CVZ (See Note) ISL6534CVZ ISL6534CR ISL6534CR ISL6534CRZ (See Note) ISL6534CRZ ISL6534EVAL2 EVAL board NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Add “ ...

Page 3

Block Diagram VCC5 30µA SS1/EN1 VCC5 30µA SS2/EN2 VCC5 30µA SS3/EN3 3.3V PGOOD COMP1 FB1 0.6V REFIN FB2 COMP2 GND 3 ISL6534 VCC VCC5 POWER 5.8V ON RESET AND CONTROL REFERENCE BIAS CURRENT 0.6V CLOCK AND SAWTOOTH GENERATOR PGOOD = ...

Page 4

Typical Application, DDRAM Controller VOLTAGE INPUTS REQUIRED VCC12 (12V) VCC (5V OR 5.8V FROM SHUNT) VIN1, VBS1 VIN2, VBS2 VIN3 VOUT1 VOUT2 VOUT1 (DDR) VTTREF VREF NOTE: Not all components are necessary in all applications. FIGURE 2. TYPICAL APPLICATION, DDRAM ...

Page 5

Typical Application, Independent Mode VOLTAGE INPUTS REQUIRED VCC12 (12V) VCC (5V OR 5.8V FROM SHUNT) VIN1, VBS1 VIN2, VBS2 VIN3 VOUT1 VOUT2 VREF (IND) VTTREF VREF NOTE: Not all components are necessary in all applications. 5 ISL6534 ISL6534 INDEPENDENT MODE ...

Page 6

Absolute Maximum Ratings Supply Voltage (VCC12 GND - 0.3V to 14.0V Supply Voltage (VCC, separate supply GND ...

Page 7

Electrical Specifications Operating Conditions: V PARAMETER ERROR AMPLIFIER (OUT1 and OUT2) Open-Loop Gain RL = 10kΩ to ground; (Note 7) Open-Loop Bandwidth CL = 100pF 10kΩ to ground; (Note 7) Slew Rate CL = 100pF 10kΩ ...

Page 8

Electrical Specifications Operating Conditions: V PARAMETER ENABLE/SOFT-START (SS/ Enable Threshold EN Rising EN falling Noise Immunity (noise de-glitch) (Note 7) Soft-Start Current I Soft-Start High Voltage End of ramp Output High Voltage To select DDR mode; (see ...

Page 9

Pin Description VCC This power pin supplies bias to the control functions. It can be connected to a nominal 5V (±5%) supply can function as a shunt regulator (nominal 5.8V), with an external pull-up resistor (nominally 150Ω to ...

Page 10

PGOOD This digital output is an open-drain pull-down device. When power is first applied to the IC, the output is pulled low, for power “Not Good”. After all 3 soft-start pins complete their ramp up with no faults (no short ...

Page 11

LG1 is shown with a pulse width shorter than LG2; this is just an arbitrary example, and it does not affect the rising edges 180 270 FIGURE 4. PHASE OF LG2 ...

Page 12

The advantage is that if either the VREF or desired output voltage changes going forward, the only board change needed is the value more resistors. The disadvantage is that since there ...

Page 13

OPEN-DRAIN LOGIC SIGNALS EN1, 2 EN3 C C SS1 SS2 FIGURE 8. 1 AND 2 ENABLED TOGETHER BUT HAVE INDEPENDENT SOFT-STARTS FULLY INDEPENDENT. The soft-start pins can share the same capacitor, to ramp them all at the same ...

Page 14

Once the power is “Good”, PGOOD will pull low if any of the 3 SS/EN pins is pulled low. Also short is detected on either switcher, then the PGOOD will pull low, for as long as the condition ...

Page 15

PERIOD (µs) FIGURE 12. TYPICAL CLOCK PERIOD vs FS_SYNC RESISTOR TO GND SYNC With multiple switching regulators running on the same board at similar, but independent frequencies, there ...

Page 16

The above formula determines how long the Soft-Start ramp time is. But since the outputs don’t turn on until the SS/EN pin reaches ~1V, that means the actual time the output ramps is only ~70% of the total SS ramp. ...

Page 17

... Choose the appropriate bandwidth and gain to meet the design goals. 4. Check with your local Intersil Field Applications for help in choosing compensation values for these special cases; improved tools are available to help calculate values and predict acceptable performance ...

Page 18

Feedback Compensation Equations This section highlights the design consideration for a voltage- mode controller requiring external compensation. To address a broad range of applications, a type-3 feedback network is recommended (see Figure 15 COMP ...

Page 19

It is recommended a mathematical model is used to plot the loop response. Check the loop gain against the error amplifier’s open-loop gain. Verify phase margin results and adjust as necessary. The following equations describe the frequency response of the ...

Page 20

For extreme cases (such as high current (>20A using parallel lower FETs) and low threshold (~1V)), one possible solution is to capacitive-couple the LGATE; Figure 18 shows one implementation. The ...

Page 21

Figure 20 shows the upper gate drive supplied by a direct connection to VCC12. This option should only be used in converter systems where the main input voltage is +5 VDC or less. The peak upper gate-to-source voltage is approximately ...

Page 22

Output Inductor Selection The output inductor is selected to meet the output voltage ripple requirements and minimize the converter’s response time to the load transient. The inductor value determines the converter’s ripple current and the ripple voltage is a function ...

Page 23

Snubbers A snubber network is a series resistor and capacitor, usually from the phase node to GND (across the lower FET used to dampen the ringing of the phase node, which can introduce noise into other parts of ...

Page 24

A comparator monitors the COMP pins, and if either one exceeds the trip point (nominal 3.3V), and stays above it for a filter time (1-2 clock pulses of the internal oscillator; 3-6µs at the nominal 300kHz; 2-4µs at 500kHz), ...

Page 25

PCB Layout Considerations General Layout Considerations As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. ...

Page 26

IC, the more they will heat each other, so keep that thermal consideration in mind. BOOT1/2 capacitors should be near their pins; the bottom to phase and diode can be a little further away separate small capacitor ...

Page 27

... Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation ...

Page 28

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

Related keywords