ISL6534CRZ Intersil, ISL6534CRZ Datasheet - Page 15

• Manufacturer Part Number: ISL6534CRZ
• Description: IC CTRLR PWM DUAL LINEAR 32QFN
• Manufacturer: Intersil

Specifications of ISL6534CRZ

• Topology: Step-Down (Buck) Synchronous (2), Linear (LDO) (1)
• Function: Any Function
• Number Of Outputs: 3
• Frequency - Switching: 300kHz ~ 1MHz
• Voltage/current - Output 1: Controller
• Voltage/current - Output 2: Controller
• Voltage/current - Output 3: Controller
• W/led Driver: No
• W/supervisor: No
• W/sequencer: Yes
• Voltage - Supply: 3.3 V ~ 12 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SYNC
With multiple switching regulators running on the same
board at similar, but independent frequencies, there may be
interference between them; a “beat” frequency can develop,
based on the difference between the two frequencies. To
avoid this situation, the ISL6534 has a synchronization
circuit that will read an external frequency, and make the
ISL6534 follow it. The typical circuit involves taking the LG
(Lower Gate) signal from another regulator, going through a
series 10kΩ resistor (to limit the current), and connecting to
the FS_SYNC pin (with no other resistors attached). Within a
few internal clock cycles, the ISL6534 will lock-in to the new
frequency, and run normally as if it were programmed to run
there. If the signal is lost for any reason, after a set number
of clock cycles, the ISL6534 will go back to its default
internal frequency. Note: Do not use the oscillator of another
regulator directly, since the ISL6534 will scale it up by 4 to
match its own internal oscillator; using the LGATE signal will
allow the ISL6534 to match its LGATE to the same
frequency. See Figure 13.
Note that the SYNC circuit expects to see a stable
frequency, and can be fooled by variations. For example, if
the gate signal used has both leading and falling edge
modulation, that might cause some confusion. Skipping
clock cycles completely may also be misinterpreted as a
much longer period. The SYNC circuit was designed to work
over a range of 300kHz to 1MHz.
FIGURE 12. TYPICAL CLOCK PERIOD vs FS_SYNC
400
350
300
250
200
150
100
50
0
1
RESISTOR TO GND
1.5
PERIOD (µs)
2
15
2.5
3
3.5
ISL6534
Application Considerations
Decoupling Capacitors
Both the VCC12 and VCC pins should have a decoupling
ceramic capacitor (typical values are 1 - 10µF), located as
near to the pin as possible, and with the GND connection as
a via to a wide GND plane. A low-value resistor in series with
the capacitor may help isolate the switching noise from the
power supply from affecting the capacitor, especially if either
pin is sharing a power supply with other noisy circuits
(adding a resistor in series with the shunt regulator resistor
gives no advantage).
SS_EN Capacitors
The basic formula for the soft-start is:
Plugging in the known values, and adjusting units, time (in
ms) = 110 * C (in µF). So, for example, a 0.1µF capacitor will
give a ramp time of 11ms, and a 1.0µF capacitor will give a
ramp time of 110ms, which is around the practical maximum
value allowed, before noise and leakage and other factors
start affecting the formula. Faster ramps are allowed, as long
as the input supplies are capable of charging the output
capacitors (and possibly the load currents, if present at
power-up), without drooping too much (for example, if either
the 5V or 12V supply is dragged down below its POR falling
trip point, because of output loading, that might indicate that
the output ramp is too fast (or perhaps bigger input
capacitors are needed, or possibly other explanations as
well).
t
where
t is the soft-start ramp time
C is the external capacitor to GND on the SS pin
dV is the voltage the ramp charges up to
(nominal value is 3.3V)
I is the charging current (nominal 30µA).
Or:
time (in ms) = 110 * C (in µF).
=
FIGURE 13. CONNECTION OF FS_SYNC TO THE LGATE OF
C
•
ISL6534
FS_SYNC
-------- -
I
dV
SS
ANOTHER SWITCHING REGULATOR
REGULATOR
OTHER
UGATE1
LGATE1
RFS
VIN1
November 18, 2005
VOUT1
FN9134.2