ISL6534CRZ Intersil, ISL6534CRZ Datasheet - Page 20

• Manufacturer Part Number: ISL6534CRZ
• Description: IC CTRLR PWM DUAL LINEAR 32QFN
• Manufacturer: Intersil

Specifications of ISL6534CRZ

• Topology: Step-Down (Buck) Synchronous (2), Linear (LDO) (1)
• Function: Any Function
• Number Of Outputs: 3
• Frequency - Switching: 300kHz ~ 1MHz
• Voltage/current - Output 1: Controller
• Voltage/current - Output 2: Controller
• Voltage/current - Output 3: Controller
• W/led Driver: No
• W/supervisor: No
• W/sequencer: Yes
• Voltage - Supply: 3.3 V ~ 12 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

back on momentarily, causing large shoot-through currents,
and hurting efficiency.
For extreme cases (such as high current (>20A using
parallel lower FETs) and low threshold (~1V)), one possible
solution is to capacitive-couple the LGATE; Figure 18 shows
one implementation. The zener reverse drop on the left
(~3V) and the forward drop of the zener on the right level
shifts the LGATE down about to about -4V when off, which
keeps Q2 off better; the downsides are the extra
components, and the lowered LGATE high voltage (shifted
from 12V down to ~8V).
The ISL6534 requires 2 N-Channel power MOSFETs for
each switcher output. These should be selected based upon
r
management requirements. The following are some
additional guidelines.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss
components; conduction loss and switching loss. The
conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs.
These losses are distributed between the two MOSFETs
according to duty factor (see the equations below). Only the
upper MOSFET has switching losses, since the FET body
diode (or optional external Schottky rectifier) clamps the
switching node before the synchronous rectifier turns on.
P
Where: D is the duty cycle = V
P
(CHANNEL
DS(ON)
LOWER
UPPER
1 OR 2)
ISL6534
+
-
VCC12
+12V
t
Fs is the switching frequency.
, gate supply requirements, and thermal
SW
= I
= I
FIGURE 18. CAPACITIVE-COUPLED LGATE
O
O
VCC12
PGND
GND
is the switching interval, and
2
2
x r
x r
DS(ON)
DS(ON)
+
D
V
BOOT
UGATE
LGATE
PGND
D
BOOT
-
x D +
x (1 - D)
C
20
BOOT
O
1
2
/V
IN
Io x V
,
IN
x t
SW
x Fs
VIN
Q1
Q2
PHASE
ISL6534
These equations assume linear voltage-current transitions
and do not adequately model power loss due the reverse-
recovery of the lower MOSFETs body diode. The
gate-charge losses are dissipated by the ISL6534 and don't
heat the MOSFETs. However, large gate-charge increases
the switching interval, t
MOSFET switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate
heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
Standard-gate MOSFETs (typically 30V breakdown and 20V
maximum gate voltage) are normally recommended for use
with the ISL6534, especially since 12V is expected to be
available to drive the gates. However, logic-level gate
MOSFETs can be used under special circumstances. The
input voltage, upper gate drive level, and the MOSFETs
absolute gate-to-source voltage rating determine whether
logic-level MOSFETs are appropriate.
Figure 19 shows the upper gate drive (BOOT pin) supplied
by a bootstrap circuit from VCC12. The boot capacitor,
C
PHASE node. This supply is refreshed each cycle to a
voltage of VCC12 less the boot diode drop (V
lower MOSFET, Q2 turns on. A logic-level MOSFET can only
be used for Q1 if the MOSFET’s absolute gate-to-source
voltage rating exceeds the maximum voltage applied to VIN
= VCC12. A a lower voltage supply (such as 5V) can also be
used for bootstrapping, which would allow for a lower gate
voltage rating; but only if the lower voltage is still high
enough to turn the upper FET on hard enough. For Q2, a
logic-level MOSFET can be used if its absolute gate-to-
source voltage rating exceeds the maximum voltage applied
to VCC12; but very low thresholds can cause problems.
(CHANNEL
BOOT
1 OR 2)
FIGURE 19. UPPER GATE DRIVE - BOOTSTRAP OPTION
ISL6534
+
-
VCC12
+12V
develops a floating supply voltage referenced to the
VCC12
PGND
GND
+
D
V
BOOT
D
BOOT
UGATE
LGATE
PGND
-
SW
which increases the upper
C
BOOT
Q1
PHASE
Q2
+5V OR +12V
D2 (OPTIONAL)
NOTE:
V
NOTE:
V
D
G-S
G-S
November 18, 2005
) when the
≈ V
≈ VCC12
CC12
FN9134.2
- V
D