ISL6534CRZ Intersil, ISL6534CRZ Datasheet - Page 25

• Manufacturer Part Number: ISL6534CRZ
• Description: IC CTRLR PWM DUAL LINEAR 32QFN
• Manufacturer: Intersil

Specifications of ISL6534CRZ

• Topology: Step-Down (Buck) Synchronous (2), Linear (LDO) (1)
• Function: Any Function
• Number Of Outputs: 3
• Frequency - Switching: 300kHz ~ 1MHz
• Voltage/current - Output 1: Controller
• Voltage/current - Output 2: Controller
• Voltage/current - Output 3: Controller
• W/led Driver: No
• W/supervisor: No
• W/sequencer: Yes
• Voltage - Supply: 3.3 V ~ 12 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCB Layout Considerations
General Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. These interconnecting impedances should be
minimized by using wide, short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding.
Figure 23 shows the critical power components of the
converter, for either output channel. To minimize the voltage
overshoot the interconnecting wires indicated by heavy lines
should be part of ground or power plane in a printed circuit
board. The components shown in Figure 23 should be
located as close together as possible. The capacitors C
and C
Locate the ISL6534 within 1 inch (or even less, if possible) of
the MOSFETs, Q1 and Q2. The circuit traces for the
MOSFETs’ gate and source connections from the ISL6534
must be sized to handle up to 1.5A peak current.
Figure 24 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Note that the “quiet”
analog-type signals (including VCC, SS/EN, FS/SYNC
shown, as well as others, such as VREF, REFOUT, and all
three of the FB resistor dividers) share a local “quiet” GND.
VCC12 decoupling cap can also share the same GND; on
the QFN package, a separate cap for each VCC12 and
PGND pin pair can help isolate some switching noise
between the channels, if placed properly (short traces to
both pins, before tying the GNDs into the common GND
plane). On the output side, the lower FET source and C
cap should share a short connection; same with the upper
FET drain, and the C
FIGURE 23. PRINTED CIRCUIT BOARD POWER AND
ISL6534
O
can each represent numerous physical capacitors.
UGATE
LGATE
PGND
GROUND PLANES OR ISLANDS
IN
cap. The output load and C
V
Q2
Q1
RETURN
IN
25
C
IN
L
O
C
O
V
OUT
OUT
IN
IN
ISL6534
share another local connection; these output GNDs are
considered “noisy”, due to the high current switching; they
should be kept away from the “quiet” GNDs near the IC.
Finally, all of these GNDs tie into one common GND plane.
Minimize any leakage current paths on each of the SS pins
and locate the capacitors, C
the internal current source is only 30µA. Provide local V
decoupling between VCC12 and PGND pins, as well as the
VCC and GND pins. Locate the capacitor, C
as practical to the BOOT pin and PHASE node (but since
PHASE is one of the noisiest signals, otherwise keep it away
from the IC area). The PGND pins are used only for the gate
drivers and other output circuitry (including the VCC12
decoupling capacitor); the GND pins are used by the VCC
pin, and the control circuitry. They should be joined at a
common point; the metal pad under the IC is a good location.
Layout Considerations for the ISL6534
The metal plate on the bottom of either the TSSOP or QFN
(MLFP) package must be soldered down to the PC board,
and sufficient plane area given for heat transfer. It is
recommended that the plane be connected to GND (pin 15
in TSSOP) and PGND (pin 18 in TSSOP), but if it is left
floating, it should NOT be tied to any other potential.
Thermal vias (at least 4) are recommended to connect to a
plane on the opposite side of the PCB (which can also be
used as a quiet GND for many of the IC components), and to
the internal GND plane, for additional heat transfer. See
Tech Brief TB379 for more details.
Decoupling capacitors should be very close to the VCC12 (to
PGND) and VCC5 (to GND) pins, with vias (if needed) to the
quiet GND plane. PGND and GND should be joined at the
metal plate.
The traces from the gate drivers to the FETs (UG1, UG2,
LG1, LG2, DRIVE3) should be short (for low resistance) and
wide (to handle large currents); the pin spacing will limit the
widths right near the package. But the closer the FETs are to
R
FIGURE 24. PRINTED CIRCUIT BOARD SMALL SIGNAL
FS
C
(QUIET) GNDs
SS
C
VCC
LAYOUT GUIDELINES
SS
VCC
FS
ISL6534
GND
VCC12
PGND
BOOT
C
ss
BOOT
+12V
close to the SS pin because
C
+12V
VCC12
D1
C
I
Q1
PHASE
+V
Q2
BOOT
IN
(NOISY) GNDs
L
November 18, 2005
O
C
O
as close
FN9134.2
CC12
V
OUT