ISL6534CRZ Intersil, ISL6534CRZ Datasheet - Page 23

• Manufacturer Part Number: ISL6534CRZ
• Description: IC CTRLR PWM DUAL LINEAR 32QFN
• Manufacturer: Intersil

Specifications of ISL6534CRZ

• Topology: Step-Down (Buck) Synchronous (2), Linear (LDO) (1)
• Function: Any Function
• Number Of Outputs: 3
• Frequency - Switching: 300kHz ~ 1MHz
• Voltage/current - Output 1: Controller
• Voltage/current - Output 2: Controller
• Voltage/current - Output 3: Controller
• W/led Driver: No
• W/supervisor: No
• W/sequencer: Yes
• Voltage - Supply: 3.3 V ~ 12 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Snubbers
A snubber network is a series resistor and capacitor, usually
from the phase node to GND (across the lower FET); it is
used to dampen the ringing of the phase node, which can
introduce noise into other parts of the circuit. In particular,
jitter on the gate drivers can be caused by disturbances that
trigger the programmable duty cycle edge of the internal
ramp generator. If noise or ringing is a problem in your
particular circuit, consider adding a snubber. Typical values
are 2.2nF for the capacitor, and 2.2Ω for the resistor. Since
the resistor may have large currents, use a 1/2W type
resistor. The order of R and C doesn’t usually matter, but
one preference is putting the resistor to GND, such that the
voltage across it can be easily measured on an oscilloscope
to represent the current. See Figure 21.
Optional Schottky Selection
An optional rectifier D2 (see Figure 19 or 20) is a clamp that
catches the negative inductor swing during the dead time
between turning off the lower MOSFET and turning on the
upper MOSFET. The diode must be a Schottky type to
prevent the lossy parasitic MOSFET body diode from
conducting. If used, connect the cathode to the phase node,
and the anode to PGND. It is acceptable to omit the diode and
let the body diode of the lower MOSFET clamp the negative
inductor swing, but efficiency will drop one or two percent as a
result. The diode's rated reverse breakdown voltage must be
greater than the maximum input voltage.
Margining and “Fine-Tuning”
Margining can be added externally to a voltage regulator, in
order to raise and/or lower the output voltage a nominal
amount, such as ±10%. The purpose might be to run the
processor at higher voltage for faster clock speeds, or to run
at lower voltages, to save power, for example.
A straightforward method involves adding two extra resistors
and two small FETs (and re-adjusting R2, depending upon
the decoding used); see Figure 22. Both resistors (RM1,
RM2) are high values (10-100kΩ) compared to R1 and R2
(~1kΩ). So when placed in parallel with R2, it lowers the
resistance of R2; pick the values for the desired amount.
Some simple logic is needed on the gates A and B to control
them; pull-up or pull-down resistors might also be needed.
FIGURE 21. SNUBBER COMPONENT SELECTION
UGATE1
LGATE1
PHASE1
23
VIN1
CSN1
RSN1
VOUT1
ISL6534
Only 3 of the 4 possible states are shown decoded. There
are other variations of this technique, but this shows the
basic principle. Since the FB are sensitive nodes, care
should be taken in the layout, to keep the extra resistors
(and the FETs to GND) near the pin.
A variation of this technique can be used without the margining
to fine tune the output voltage, when two 1% resistors (R1, R2)
can’t give the exact value desired. Simply use a much higher
value resistor in parallel with either R1 or R2 (or both) to fine-
tune the value; a 100-1 ratio in resistor values will be able to
change the voltage by roughly 1%; that might be good enough.
Short-Circuit Protection
The ISL6534 does not have the typical overcurrent
protection used by many of the Core Processor IC’s.
Instead, it has a simple and inexpensive method of
protection. But it is important for the user to understand the
method used, and the limitations of that method.
There are no sense pins available on the ISL6534. This
means that the many standard ways of sensing output
current (sense resistors, FET r
are not possible, without adding a lot of external
components. There are also no PHASE pins available.
Monitoring undervoltage (by sensing drops on the FB pins,
or on the outputs) was not done.
The only method of protection for the two switching
regulators is to monitor the COMP1 and COMP2 pins for
overvoltage. What happens on a short-to-GND on the
output? As the output voltage is dragged down, the FB pin
should start to follow, since it is usually just a resistor divider
from the output. The loop detects that the FB pin is lower
than the Error-Amp reference, and the COMP voltage will
rise to try to equalize them; that will increase the duty-cycle
of the upper FET gate driver (which allows more time to pull
the output voltage higher). If the short is hard enough, the
COMP pin will rise higher and the duty cycle will increase
further. If the short is still too hard, at some point the COMP
pin output will go out of range, the duty cycle will hit the
maximum, and the loop can no longer effectively try any
harder. This is the point at which an overcurrent condition is
FIGURE 22. MARGINING COMPONENT SELECTION
A OFF, B OFF
A OFF, B ON
A ON, B ON
RM1, RM2 >> R1, R2
VOUT1
10% HIGH
NOMINAL
10% LOW
R1
DS(ON)
A
RM2
, Inductor DCR, etc.)
R2
November 18, 2005
COMP1
FB1
RM1
B
FN9134.2