ISL6534CRZ Intersil, ISL6534CRZ Datasheet - Page 16

• Manufacturer Part Number: ISL6534CRZ
• Description: IC CTRLR PWM DUAL LINEAR 32QFN
• Manufacturer: Intersil

Specifications of ISL6534CRZ

• Topology: Step-Down (Buck) Synchronous (2), Linear (LDO) (1)
• Function: Any Function
• Number Of Outputs: 3
• Frequency - Switching: 300kHz ~ 1MHz
• Voltage/current - Output 1: Controller
• Voltage/current - Output 2: Controller
• Voltage/current - Output 3: Controller
• W/led Driver: No
• W/supervisor: No
• W/sequencer: Yes
• Voltage - Supply: 3.3 V ~ 12 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The above formula determines how long the Soft-Start ramp
time is. But since the outputs don’t turn on until the SS/EN
pin reaches ~1V, that means the actual time the output
ramps is only ~70% of the total SS ramp. Figure 9 shows an
example; SS1/EN1 ramps from 0 and 1V, before the VOUT1
ramp starts; but they both end at the same time. If the SS
ramp was 3.3ms long, the output ramp would be about
2.3ms long.
Each of the three regulators can have its own independent
ramp rate, as well as their own independent enable function
(pulling one of the SS/EN pins below 1V nominal will shut
down that output). Two or three pins can be tied together to
share a common ramp and enable; but there are now two or
three times the current charging a single cap, so the formula
should be adjusted accordingly. If you need the same ramp
rate, but separate enable functions, then don’t share the
capacitor; just use the same value capacitor on each, which
will still allow independent enabling. If you need different
ramp rates, but want to share a single enable signal, you will
probably need to connect a separate pull-down FET to each
pin, and just drive their gates from a common signal, or use
diodes to isolate a single FET to multiple pins (as previously
shown in Figures 7 and 8).
VREF/REFOUT Capacitors
The VREF output may require a small capacitor to GND to
remain stable; 1.0µF is recommended. If the output is not
used (for example, in DDR mode, where if VOUT1 is divided
down for REFIN); it could be left open, but the additional
noise and current draw may be objectionable. So even then,
a capacitor is recommended.
The REFOUT output is similar; a 0.1µF capacitor is
recommended.
Linear (VOUT3) Component Selection
Once the VIN3 and VOUT3 levels are defined, the NFET is
chosen to handle the output load current and the power
dissipation it creates. The power is determined by:
Even if the FET is in a good thermal package (such as a
D-PAK), the mounting of the FET will determine how much
power dissipation is allowed. If simply placed on a pad on an
FR4 board, the dissipation will be limited by the area of the
pad; the more area, the lower the temperature will be. The
recommendation is to use large plane areas, as well as
thermal vias to the back of the board, plus additional area
there, if possible. Even then, power dissipation is usually
limited to 1W or so, which would give 1A (assuming a 1V
drop from VIN3 to VOUT3).
It is not recommended to parallel two FETs in order to get
higher current or to spread out the heat; the FETs would
need to be well-matched in order to share the current equally
without any additional circuitry. In addition, the DRIVE3 pin
output was not sized to drive multiple FET gates; it may take
Power
=
(
VIN3 VOUT3
–
) ILOAD
•
16
ISL6534
longer to charge or discharge the gates during transients.
Similar problems will occur if two FETs are placed in series;
the currents will be equal, but the voltage across each will
not match without additional circuitry. Acceptable solutions
include adding a heat sink or airflow, finding or creating an
input voltage closer to the output voltage, reducing the load
current (or raising the output voltage), adding a 2nd
complete linear output (and splitting the load between the
two) or replacing the linear with a switcher.
The output capacitor C
filtering and transient response needs. However, the output
capacitor also affects the stability of the regulator, so the
choice is limited to a range of acceptable values, which
include the capacitance and its ESR (Effective Series
Resistance). See Figure 14.
The input capacitance C
supply from changing too much when the output current load
changes; this is related to transient response.
The resistor ratio is chosen to divide the desired output
voltage down to make the FB3 pin = 0.6V. First choose R1;
1kΩ is a good typical value. In the equation below, plug in
the value of FB3 from the Specification Table, and the
desired VOUT3 value, and solve for R2.
Compensation components R3 and C3 are chosen to make
the output stable under the conditions being used. Choose
the values to add a zero around 30kHz to cancel a pole.
Values of 4.75K and 6800pF are a good starting point.
If the Linear output is not used, then tie DRIVE3 to FB3 to
terminate them; no other components are needed. There are
then several options for SS/EN3. If PGOOD is not being
used, SS/EN3 can be tied to GND to disable the linear (and
PGOOD). If you need PGOOD to be active for the switchers
VOUT1 and VOUT2, then SS/EN3 can be left open for a
very fast ramp, or it can be tied to tied to SS/EN1 or SS/EN2
(but remember that SS/EN3 adds charging current, so make
the cap bigger). It is not recommended to tie SS/EN3 to
VCC.
R2
FIGURE 14. LINEAR (VOUT3) REGULATOR COMPONENT
=
---------------------------------------
VOUT3 FB3
FB3 R1
⋅
SELECTION
DRIVE3
–
FB3
OUT3
IN3
R3
is chosen to keep the input
C3
should be chosen for output
R2
R1
VIN3
COUT3
CIN3
VOUT3
November 18, 2005
FN9134.2