ISL6534CRZ Intersil, ISL6534CRZ Datasheet - Page 26

• Manufacturer Part Number: ISL6534CRZ
• Description: IC CTRLR PWM DUAL LINEAR 32QFN
• Manufacturer: Intersil

Specifications of ISL6534CRZ

• Topology: Step-Down (Buck) Synchronous (2), Linear (LDO) (1)
• Function: Any Function
• Number Of Outputs: 3
• Frequency - Switching: 300kHz ~ 1MHz
• Voltage/current - Output 1: Controller
• Voltage/current - Output 2: Controller
• Voltage/current - Output 3: Controller
• W/led Driver: No
• W/supervisor: No
• W/sequencer: Yes
• Voltage - Supply: 3.3 V ~ 12 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

the IC, the more they will heat each other, so keep that
thermal consideration in mind.
BOOT1/2 capacitors should be near their pins; the bottom to
phase and diode can be a little further away. If a separate
small capacitor is used for the bootstrap supply (if different
than either VIN or VCC12), it should be located next to the
bootstrap diode anode.
Other traces to keep short include:
• FB1/2/3: the resistor dividers should be near the IC; via (if
• Resistor dividers used for references (from VREF or
• COMP1/2: ALL of the compensation components should
• SS/EN capacitors should be near pin, with vias (if needed)
• FS_SYNC resistor (if needed) should be near pin, with a
• Output capacitors should be close to the loads, where the
• The VIN plane should be large to heatsink the upper FET
needed) to quiet GND plane; the signal from the VOUT
can travel, since it is low impedance. The VOUT should be
taken as close as possible to the load for best regulation,
and the trace to the feedback resistor divider should be
isolated from any load current.
VOUT or to REFIN) should be near the REFIN input; the
bottom resistor tied to quiet GND.
be close to these pins (as well as FB1/2 pins), with vias (if
needed) to the quiet GND plane. The FB divider should
NOT be near the output, with FB routed back to the IC; the
FB trace can act as an antenna and pick up noise that will
adversely affect performance. Route the VOUT signal
instead, and connect it to the components near the IC.
to quiet GND plane.
via (if needed) to quiet GND. Do not leave the pin open;
connect to GND (through a zero ohm resistor or a short
trace) for default 300 kHz operation. The GND connection
(for either the resistor or default) should be kept away from
the Power GND of the output FETs; this is especially
important because the FS_SYNC pin location is near the
channel 2 switcher. Noise picked up can cause jitter in
both switcher outputs.
filtering will help most; small ceramic capacitors (~1µF) in
parallel help for high frequency transients. Input capacitors
should be near the VIN pins of the FETs; the input
capacitor GNDs should be close to the lower FET GND as
well.
effectively, since the drain pin is usually the thermal node.
By the same reasoning then, the phase node plane should
also be large, since the lower FET drain is connected
there. However, the phase node plane couples high
frequency switching noise to other levels nearby, so it
should be minimized for that reason. And don’t route any
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ISL6534
• GND: All of the “quiet” analog functions (mostly the top,
Several placement approaches are possible:
• IC and output FETs, caps, and inductors on top level
• All components on top level, with output components
• In either case, it is recommended that the IC and its
sensitive or high impedance signals over the phase
planes.
left and bottom of Figure 2 or 3) should share a common
IC GND, tied to the metal pad, and the GND and PGND
pins. These include components associated with the
following pins: VCC, VCC12, FB1, FB2, FB3, REFIN,
REFOUT, VREF, FS_SYNC, SS1/EN1, SS2/EN2,
SS3/EN3, GND, PGND. The metal pad under the IC can
be extended as a local top (or bottom) layer GND plane; if
thermal vias are used to a plane on the opposite layer, that
too can be used as a local GND plane. Vias to the GND
plane only are still acceptable, as long as they are local to
the IC area. Each output section should have its own local
power GND area, away from the IC GND. Finally, all of the
GND’s can be connected together.
(tallest heights); most of the miscellaneous resistors and
capacitors (all small heights) on the bottom level; this
allows most of the analog components to be grouped near
the pins, with vias to the pins. The IC can also be placed
on the bottom.
facing pins 13-24 side of IC, and input components facing
pins 1-12. This has less flexibility for close placement of
the analog components, but it is still easy to accomplish,
as long as there aren’t too many other board size or shape
constraints.
associated components have a local GND, separated from
the output stage GNDs, but connected through the GND
plane.
November 18, 2005
FN9134.2