ISL6534CRZ Intersil, ISL6534CRZ Datasheet - Page 19

• Manufacturer Part Number: ISL6534CRZ
• Description: IC CTRLR PWM DUAL LINEAR 32QFN
• Manufacturer: Intersil

Specifications of ISL6534CRZ

• Topology: Step-Down (Buck) Synchronous (2), Linear (LDO) (1)
• Function: Any Function
• Number Of Outputs: 3
• Frequency - Switching: 300kHz ~ 1MHz
• Voltage/current - Output 1: Controller
• Voltage/current - Output 2: Controller
• Voltage/current - Output 3: Controller
• W/led Driver: No
• W/supervisor: No
• W/sequencer: Yes
• Voltage - Supply: 3.3 V ~ 12 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

It is recommended a mathematical model is used to plot the
loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G
compensation (G
COMPENSATION BREAK FREQUENCY EQUATIONS
Figure 17 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F
amplifier. The closed loop gain, G
log graph of Figure 17 by adding the modulator gain, G
dB), to the feedback compensation gain, G
equivalent to multiplying the modulator transfer function and the
compensation transfer function and then plotting the resulting
gain.
G
F
F
FIGURE 17. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Z1
Z2
MOD
G
G
FB
CL
0
=
=
LOG
f ( )
f ( )
f ( )
------------------------------- -
2π R2 C1
-------------------------------------------------- -
2π
20
log
=
=
=
⋅
⋅
⋅
(
d
----------------------------- -
----------------------------------------------------- - ⋅
s f ( ) R1
---------------------------------------------------------------------------------------------------------------------------- -
(
G
R1
1


1
MAX
R2
------- -
R1
1
MOD
V
⋅
+
+
+
1


OSC
⋅
s f ( ) R3 C3
s f ( ) R2 C1
R3
FB
⋅
f ( ) G
V
F
) C3
⋅
) and closed-loop response (G
⋅
IN
Z1
⋅
⋅
⋅
(
F
C1
1
F
⋅
P2
LC
Z2
FB
----------------------------------------------------------------------------------------
1
+
⋅
⋅
+
+
s f ( )
against the capabilities of the error
f ( )
C2
s f ( )
)
F
F
F
F
19
⋅
⋅
CE
P1
)
P1
P2


(
⋅
R1
1
(
CL
1
E
+
=
=
F
+
+
s f ( ) R2
0
+
, is constructed on the log-
---------------------------------------------- -
2π R2
------------------------------- -
2π R3 C3
where s f ( )
F
s f ( ) E C
R3
D
20
P2
) C
⋅
⋅
⋅
log
) C3
⋅
G
⋅
1
⋅
MOD
CL
COMPENSATION GAIN
d
---------------------------------
FB
OPEN LOOP E/A GAIN
,
+
⋅
⋅
CLOSED LOOP GAIN
MAX V
G
⋅
⋅
1
--------------------- -
C1
s


V OSC
C1 C2
MODULATOR GAIN
MOD
(in dB). This is
--------------------- -
C1
2
C1 C2
), feedback
f ( ) L C
FREQUENCY
+
⋅
=
⋅
+
⋅
C2
⋅
2π f j
IN
C2
CL
⋅
⋅ ⋅


G
MOD


):
FB
(in
ISL6534
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin. The mathematical model
presented makes a number of approximations and is
generally not accurate at frequencies approaching or
exceeding half the switching frequency. When designing
compensation networks, select target crossover frequencies
in the range of 10% to 30% of the switching frequency, F
FET Selection (VOUT1, VOUT2)
The typical FET expected to be used will have a low r
(5-10mΩ) and a low V
1-2V). It can be packaged in a thermally enhanced SO-8 IC
package (where the drain leads are thermally connected to
the leadframe under the die, or similar approaches), or even
in more conventional power packages (D-PAK). If the FETs
are surface mounted to the PCB, with only the area of the
power planes to conduct the heat away, then the maximum
load current will be limited by the thermal ratings under those
conditions. Using conventional heatsinks or sufficient airflow
can extend the limit of dissipation.
FETs can be paralleled for higher currents; this spreads the
heat between the FETs, which helps keep the temperature
lower. However, the gate driver is now driving twice the gate
capacitance, so there will be more dissipation in the ISL6534
gate drivers. It is recommended that parallel FETs be the
same part number; even though they may not match exactly,
it is more likely than using two different parts. In particular,
the r
sharing; the gate threshold and the internal gate resistance
helps determine the turn on and off characteristics.
Typical values for maximum current (based on 8-pin SOIC
FETs surface-mounted on PCB, with no heatsinks or airflow)
are 5A for a dual FET; 10A for single FETs for upper and
lower; and 20A for two FETs in parallel for both upper and
lower. These are just rough numbers; many factors affect it,
such as PCB board area available for heatsinking planes,
how close other dissipative devices are, etc.
In general (and especially for short UGATE duty cycles, such
as converting 12V input down to 1V or 2V outputs), the
upper FET should be chosen to minimize the Gate charge,
since switching losses dominate. Since the lower FET is on
most of the time, low r
consideration for it.
Note that the LGATE driver is sourced from the VCC12
input; it is not necessary to use a very low threshold lower
FET device; for example, the difference in r
a 1V and 2V threshold, with a 12V gate voltage is very small;
the curve for r
around 10V. And, in fact, a too-low threshold voltage can
cause a transition problem. As LGATE goes to GND to turn
off, (and UGATE starts to turn on), it only takes a couple of
volts of noise or ringing or coupling in the LGATE to turn it
DS(ON)
of each helps determine the relative current
DS(ON)
versus V
GS
DS(ON)
(Gate-to-source threshold voltage;
should be the main
GS
is already flattening out
DS(ON)
November 18, 2005
between
DS(ON)
FN9134.2
SW
.