EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 147
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (13Mb)
DS785UM1
Note: The value in the register is the actual coefficient minus one.
Note: The value in the register is the actual coefficient minus one.
Note: This means that PLL2 FOUT is programmed to be 48,000,000 Hz on startup.
Note: The value in the register is the actual coefficient minus one.
PLL2_X2FBD2:
PLL2_X1FBD1:
PLL2_PS:
PLL2_EN:
nBYP2:
USBDIV:
Copyright 2007 Cirrus Logic
These 6 register bits set the first feedback divider bits for
PLL2. On power-on-reset the value is set to 11000b (24
decimal).
These 5 register bits set the second feedback divider bits
for PLL2. On power-on-reset the value is set to 11000b (24
decimal).
These two bits determine the final divide function on the
VCO clock signal in PLL2.
00 - Divide by 1
01 - Divide by 2
10 - Divide by 4
11 - Divide by 8
On power-on-reset these bits are reset to 11b (3 decimal).
This bit enables PLL2. If set, PLL2 is enabled. If this bit is
zero, PLL2 is disabled. On power-on-reset the value is set
to 0b.
This bit selects the clock source for the processor clock
dividers. If set, PLL2 is the clock source. If this bit is set to
zero, the external clock is the clock source. On power-on-
reset, this bit defaults to 0b.
These four bits set the divide ratio between the PLL2
output and the USB clock.
0000 - Divide by 1
0001 - Divide by 2
0010 - Divide by 3
0011 - Divide by 4
0100 - Divide by 5
0101 - Divide by 6
0110 - Divide by 7
0111 - Divide by 8
On power-on-reset these bits are reset to 0000b.
1111 - Divide by 1
1011 - Divide by 12
1110 - Divide by 15
1000 - Divide by 9
1001 - Divide by 10
1010 - Divide by 11
1100 - Divide by 13
1101 - Divide by 14
EP93xx User’s Guide
System Controller
5-21
5
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