EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 706
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 706 of 824
- Download datasheet (13Mb)
22
AC97RGIS
22-18
AC’97 Controller
EP93xx User’s Guide
31
15
Address:
Definition:
Bit Descriptions:
30
14
29
13
28
12
0x8088_008C - Read Only
Raw Global Interrupt Status Register. The AC’97 raw global interrupt status
register is a read/write register that gives the status of various functions
outside of the FIFO functionality within the controller.
RSVD:
SLOT2TXCOMPLETE:Set when the AC97S2Data register has completed
CODECREADY:
WINT:
GPIOINT:
GPIOTXCOMPLETE:GPIO Transmission Complete. Set when a new value to
SLOT2RXVALID: The AC97S2Data register has new data that has not been
SLOT1TXCOMPLETE:Set when the AC97S1Data register has completed
RSVD
27
11
26
10
25
9
Copyright 2007 Cirrus Logic
24
Reserved. Unknown During Read.
This bit is set to “1” during a wakeup when the codec
RAW Wake-up Interrupt Status. If this bit is set to “1”. The
The GPIOINT shows the raw status of the GPIOINT bit
8
transmission. This bit is cleared when data is in the
register to be transmitted.
indicates that it is ready by setting bit 15 of Slot0. It is
cleared by writing to Bit1 of the AC97EOI Register.
RAW Wake-up interrupt is asserted. This bit is cleared
with a write to the AC97EOI register.
(slot 12 bit 0) in the receive frame, which is stored in
the AC97S12Data register. This bit is cleared when
the AC97S12Data register is read.
the AC97S12Data register has completed
transmission. Cleared when data is placed in the
register to be transmitted.
read. Reading the data in the AC97S2Data register
clears this bit.
transmission. This bit is cleared when data is written
to the AC97S1Data register to be transmitted.
23
7
RSVD
COMPLETE
SLOT2TX
22
6
CODEC
READY
21
5
WINT
20
4
GPIO
INT
19
3
COMPLETE
GPIOTX
18
2
SLOT2RX
VALID
17
1
DS785UM1
COMPLETE
SLOT1TX
16
0
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