EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 237
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 237 of 824
- Download datasheet (13Mb)
RasterSWLock
DS785UM1
31
15
Address: 0x8003_007C
Default: 0x0000_0000
Definition: Raster Software Lock register
Bit Descriptions:
30
14
29
13
28
12
PCLKEN:
EN:
RSVD:
SWLCK:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Pixel Clock Enable - Read/Write
The value written to this bit selects whether the pixel clock
or smart panel clock are output to the SPCLK pin, or not:
0 - SPCLK pin at high impedance
1 - PCLK or SCLK active on SPCLK pin
The PIFEN bit above selects PCLK vs. SCLK.
Enable Video State Machine - Read/Write
The value written to this bit selects whether the video state
machine is enabled, or not:
0 - Video state machine off
1 - Video state machine enabled
Reserved - Unknown during read
Software Lock - Read/Write
WRITE: Writing 0X0000_00AA to this register will unlock
all locked registers until the next block access.
READ: During a read operation, SWLCK[0] has this
meaning:
1 - Unlocked for current bus access
0 - Locked
The Read feature of the RasterSWLock register is used for
testing the locking function.
Raster Engine With Analog/LCD Integrated Timing and Interface
24
8
RSVD
23
7
22
6
21
5
20
4
SWLCK
19
3
EP93xx User’s Guide
18
2
17
1
16
7-55
0
7
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