EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 701
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 701 of 824
- Download datasheet (13Mb)
DS785UM1
AC97RISRx
31
15
Address:
Definition:
Bit Descriptions:
30
14
29
13
28
12
TXBUSY:
TXFF:
RXFF:
TXFE:
RXFE:
AC97RISR1 - 0x8088_0010 - Read Only
AC97RISR2 - 0x8088_0030 - Read Only
AC97RISR3 - 0x8088_0050 - Read Only
AC97RISR4 - 0x8088_0070 - Read Only
Raw Interrupt Status. The AC97ISR registers are the raw Interrupt status
registers for the controller FIFOs. All bits are cleared to zero on reset except
for the TCIS as the FIFO and shift register should both be empty. Any write to
this register clears the overrun error.
RSVD:
RIS:
TIS:
27
11
26
10
RSVD
Copyright 2007 Cirrus Logic
25
9
TXBUSY is set when TEN = “1” AND there is data in the
FIFO, OR when data from this FIFO is being sent in the
current frame.
TXBUSY is cleared at the start of the next frame following
the assertion of the corresponding channel’s TXFE flag
(the value of TEN is irrelevant).
Transmit FIFO full flag, active HIGH.
This bit is asserted HIGH if the transmit FIFO is full.
Receive FIFO full flag, active HIGH.
This bit is asserted HIGH if the receive FIFO is full.
Transmit FIFO empty flag, active HIGH.
This bit is asserted HIGH if the transmit FIFO is empty.
Receive FIFO empty flag, active HIGH.
This bit is asserted HIGH if the receive FIFO is empty.
Reserved. Unknown During Read.
RX Interrupt Status - This bit is set to “1” if the receive
FIFO becomes half full.
TX Interrupt Status - This bit is set to “1” if the transmit
FIFO becomes half empty.
24
8
RSVD
23
7
22
6
21
5
20
4
RIS
19
3
EP93xx User’s Guide
TIS
18
2
AC’97 Controller
RTIS
17
1
22-13
TCIS
16
0
22
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