EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 798

• Manufacturer Part Number: EP9301-IQZ
• Description: 32-Bit Microcontroller IC
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9301-IQZ

• Controller Family/series: (ARM9)
• Core Size: 32 Bit
• A/d Converter: 12 Bits
• Supply Voltage: 3.3V
• No. Of I/o Pins: 24
• Mounting Type: Surface Mount
• Operating Temperature Min: -40°C
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Speed: 166MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1250

28
28-8
GPIO Interface
EP93xx User’s Guide
MCBVD[2:1]
EGPIO[15:8]
IDEDA[2:0]
EGPIO[7:0]
COL[7:0]
DD[15:12]
ROW[7:0]
MCD[2:1]
IDECS1n
IDECS0n
SLA[1:0]
DD[11:8]
GRLED
RDLED
READY
EECLK
EEDAT
DIORn
DD[7:0]
1. IDEDA[2:0], IDECS0n, IDECS1n, and DIORn are IDE control pins.
2. VS2, VS1, MCBVD[2:1], MCD[2;1], READY, and WP are PCMCIA pins.
3. SLA[1:0] are the PCMCIA voltage control pins.
4. DD[15:0] are the IDE data pins. DD[11:8] has no GPIO pin mapping.
5. GRLED is the Green LED pin.
6. RDLED is the Red LED pin.
7. EECLK is the EEPROM clock pin.
8. EEDAT is the EEPROM data pin.
9. ROW[7:0] are the Key Matrix row pins.
Name
VS2
VS1
WP
Pin
2
2
2
1
7
8
5
6
2
10
3
4
2
1
1
9
4
1
2
IDEDA[2:0]
Function
ROW[7:0]
DD[15:12]
Port G3:2
Port F4:3
Port F2:1
IDECS1n
IDECS0n
COL[7:0]
Default
DD[11:8
Port E0
Port E1
Port G0
Port G1
DD[7:0]
Port F7
Port F6
Port F5
Port F0
DIORn
Port A
Port B
Table 28-4. EP9315 GPIO Port to Pin Map
Function in
IDEDA[2:0]
DD[15:12]
Port G3:2
Port F4:3
Port F2:1
IDECS1n
IDECS0n
Copyright 2007 Cirrus Logic
DD[11:8]
Port G0
Port G1
Port E0
Port E1
Port F7
Port F6
Port F5
Port F0
DD[7:0]
GonK
DIORn
Mode
Port C
Port D
Port A
Port B
Function in
DD[15:12]
ROW[7:0]
Port G3:2
Port F4:3
Port F2:1
Port E7:5
EonIDE
COL[7:0]
DD[11:8]
Port G0
Port G1
Port E0
Port E1
Port F7
Port F6
Port F5
Port F0
Port E4
Port E3
Port E2
DD[7:0]
Mode
Port A
Port B
Function in
IDEDA[2:0]
ROW[7:0]
Port G3:2
IDECS1n
IDECS0n
Port G7:4
GonIDE
Port F4:3
Port F2:1
COL[7:0]
DD[11:8]
Port G0
Port G1
DD[7:0]
Port E0
Port E1
Port F7
Port F6
Port F5
Port F0
Mode
DIORn
Port A
Port B
Function in
IDEDA[2:0]
DD[15:12]
Port G3:2
ROW[7:0]
Port F4:3
Port F2:1
IDECS1n
IDECS0n
HonIDE
COL[7:0]
DD[11:8]
Port G0
Port G1
Port E0
Port E1
Port F7
Port F6
Port F5
Port F0
DIORn
Mode
Port A
Port B
Port H
DS785UM1