EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 388
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
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Part Number
Manufacturer
Quantity
Price
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9
TXBufThrshld
9-86
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
31
15
Address:
Suggested Value:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
30
14
29
13
RSVD
RSVD
28
12
RDST:
0x8001_00D4 - Read/Write
0020_0010
0x0000_0000
Unchanged
Transmit Buffer Threshold register. The transmit buffer thresholds are used to
set a limit on the amount of empty space allowed in the transmit FIFO before a
bus request will be scheduled. When the number of empty words in the FIFO
exceeds the threshold value, the Descriptor Processor will schedule a bus
request to transfer data. The actual posting of the bus request may be delayed
due to lack of resources in the MAC, such as no active transmit descriptor.
The lower two bits of the thresholds are always zero.
RSVD:
TDHT:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Receive Data Soft Threshold. The hard and soft threshold
work in exactly the same manner except one. The soft
threshold will not cause a bus request to be made if the
bus is currently in use, but only when it is deemed to be
idle (no transfers for four AHB clocks). The hard threshold
takes effect immediately, regardless of the state of the bus.
This operation allows for more efficient use of the AHB bus
by allowing smaller transfers to take place when the bus is
lightly loaded and requesting larger transfers only when
the bus is more heavily loaded.
Reserved. Unknown During Read.
Transmit Data Hard Threshold.
24
8
23
7
22
6
TDHT
TDST
21
5
20
4
19
3
18
2
17
0
1
0
DS785UM1
16
0
0
0
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