EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 151
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 151 of 824
- Download datasheet (13Mb)
DeviceCfg
DS785UM1
SWRST
HC3IN
31
15
Address:
Default:
Definition:
Bit Descriptions:
HC3EN
D1onG
30
14
D0onG
HC1IN
29
13
HC1EN
IonU2
28
12
0x8093_0080 - Read/Write, Software locked
0x0000_0000
Device Configuration Register. This register controls the operation of major
system functions.
RSVD:
0:
SHena:
KEYS:
ADCPD:
RAS:
RasOnP3:
HonIDE
GonK
27
11
GonIDE
TonG
26
10
Copyright 2007 Cirrus Logic
MonG
PonG
25
9
Reserved. Unknown During Read.
This bit must be written as “0”.
Standby/Halt enable. When 1, allows the system to enter
Standby or Halt on a read from the Standby and Halt
registers, respectively.
Key matrix inactive.
1 - Key Matrix controller inactive,
0 - Key Matrix controller active.
ADC Power Down.
1 - ADC and clocks are powered down.
0 - ADC and clocks are active. ADCPD must be zero for
normal touch screen operation and for direct ADC
operation.
Raster inactive.
1 - Disables video pixel clock to most of the Raster engine,
0 - Normal video clock to Raster engine.
Raster On SDRAM Port 3.
1 - The Raster video refresh SDRAM accesses use the
system primary AHB to get video data.
0 - Raster video refresh uses the private AHB on SDRAM
Port 0.
EonIDE
U3EN
24
8
CPENA
I2Son
SSP
23
7
A2onG
I2Son
AC97
22
6
A1onG
21
5
0
RASOn
U2EN
P3
20
4
EXVC
RAS
19
3
EP93xx User’s Guide
ADCPD
U1EN
System Controller
18
2
KEYS
TIN
17
1
SHena
RSVD
5-25
16
0
5
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