EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 540
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
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Part Number
Manufacturer
Quantity
Price
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- Download datasheet (13Mb)
14
UART1RXSts
14-18
UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
0x808C_0004 - Read/Write
0x0000_0000
UART1 Receive Status Register/Error Clear Register. Provides receive status
of the data value last read from the UART1Data. A write to this register clears
the framing, parity, break and overrun errors. The data value is not important.
Note that BE, PE and FE are not used for synchronous HDLC.
RSVD:
OE:
BE:
PE:
27
11
26
10
RSVD
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
Overrun Error. This bit is set to “1” if data is received and
the FIFO is already full. This bit is cleared to “0” by a write
to UART1RXSts. The FIFO contents remain valid since no
further data is written when the FIFO is full. Only the
contents of the shift register are overwritten. The data
must be read in order to empty the FIFO.
Break Error. This bit is set to 1 if a break condition was
detected, indicating that the received data input was held
LOW for longer than a full-word transmission time (defined
as start, data, parity and stop bits). This bit is cleared to 0
after a write to UART1RXSts. In FIFO mode, this error is
associated with the character at the top of the FIFO. When
a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the receive
data input goes to a 1 (marking state) and the next valid
start bit is received.
Parity Error. When this bit is set to 1, it indicates that the
parity of the received data character does not match the
parity selected in UART1LinCtrlHigh (bit 2). This bit is
cleared to 0 by a write to UART1RXSts. In FIFO mode,
this error is associated with the character at the top of the
FIFO.
24
8
RSVD
23
7
22
6
21
5
20
4
OE
19
3
BE
18
2
PE
17
1
DS785UM1
FE
16
0
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