EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 149
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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BusMstrArb
DS785UM1
31
15
Address:
Definition:
Bit Descriptions:
30
14
RSVD
29
13
Priority Number
28
12
0x8093_0054 - Read/Write
The Bus Master arbitration register (BusMstrArb) is used to configure the AHB
master priority order.
RSVD:
PRI_ORD:
PRI_CORE:
DMA_ENIRQ:
1
2
3
4
5
6
27
11
RSVD
(Reset value)
Raster Cursor
26
10
PRIOR 00
ARM920T
Raster
Table 5-6. Priority Order for AHB Arbiter
MAC
DMA
USB
Copyright 2007 Cirrus Logic
ENFIQ
MAC
25
9
Reserved. Unknown During Read.
Used to set the priority of the AHB arbiter. The priority
order is shown in
When this bit is set the Core will become highest priority
following a grant to one of the following: Raster, Raster
Cursor, MAC, USB and DMA. If the Core then requests the
bus, it is then placed in the priority order selected by
PRI_ORD after it is granted, until one of the above
masters is granted the bus, and is placed on top of the
priority scheme.
When set the arbiter will degrant DMA from the AHB bus
and will ignore subsequent requests from DMA if an IRQ is
active. When IRQ is cleared the DMA request is allowed
again. There is no impact on other masters. Reset to 0.
ENIRQ
MAC
24
8
RSVD
Raster Cursor
PRIOR 01
ARM920T
ENFIQ
Raster
USH
MAC
DMA
USB
23
7
ENIRQ
USH
22
Table
6
ENFIQ
DMA_
Raster Cursor
21
5-6. This field resets to 00.
5
PRIOR 10
ARM920T
Raster
DMA
MAC
USB
ENIRQ
DMA_
20
4
CORE
PRI
19
3
Raster Cursor
EP93xx User’s Guide
PRIOR 11
ARM920T
RSVD
Raster
System Controller
18
DMA
MAC
USB
2
17
1
PRI_ORD
16
5-23
0
5
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