EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 244

32-Bit Microcontroller IC

EP9301-IQZ

Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9301-IQZ

Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
Other names
598-1250

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9301-IQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
7
7-62
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
DAT:
Copyright 2007 Cirrus Logic
Smart Panel R/W and RS signals must be implemented
via GPIOs and controlled via software. The difference
between the CNT[3:0] value and the ESTRT[3:0] value is
what guarantees set up time for these GPIO signals to the
Smart Panel before the rising edge of the E enable signal
on the E pin.
Data - Read Only
This parallel interface data is input to the EP93xx
processor from the Smart Panel during a read cycle (see
RD bit in the
bits from the Smart Panel are loaded into this DAT field,
respectively, on the falling edge of the ‘E’ enable control
signal on the E pin.
Writing PIFEN = ‘1’ to the
the signals on these pins for Parallel Interface (Smart
Panel) operation:
V_CSYNC --> D7 (Smart Panel)
HSYNC --> D6
BLANK --> D5
P17 --> D4
P3 --> D3
P[2:0] --> D[2:0]
SPCLK --> E
Smart Panel R/W and RS signals must be implemented
via GPIOs and controlled via software.
ParllIfOut
register for read cycle). The D[7:0]
VideoAttribs
register redefines
DS785UM1

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