EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 574
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
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Manufacturer
Quantity
Price
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15
UART2DMACtrl
15-16
UART2
EP93xx User’s Guide
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
ILPDV:
0x808D_0028 - Read/Write
0x0000_0000
UART DMA Control Register
RSVD:
DMAERR:
TXDMAE:
RXDMAE:
27
11
26
10
Copyright 2007 Cirrus Logic
RSVD
25
9
IrDA Low Power Divisor bits [7:0]. 8-bit low-power divisor
value. These bits are cleared to 0 at reset. The divisor
must be chosen so that the relationship
1.42 MHz < IrLPBaud16 < 2.12 MHz is maintained, which
results in a low power pulse duration of 1.41–2.11 μs
(three times the period of IrLPBaud16). The minimum
frequency of IrLPBaud16 ensures that pulses less than
one period of IrLPBaud16 are rejected, but that pulses
greater than 1.4 μs are accepted as valid pulses. Zero is
an illegal value. Programming a zero value will result
in no IrLPBaud16 pulses being generated.
Reserved. Unknown During Read.
RX DMA error handing enable. If 0, the RX DMA interface
ignores error conditions in the UART receive section. If “1”,
the DMA interface stops and notifies the DMA block when
an error occurs. Errors include break errors, parity errors,
and framing errors.
TX DMA interface enable. Setting to “1” enables the
private DMA interface to the transmit FIFO.
RX DMA interface enable. Setting to “1” enables the
private DMA interface to the receive FIFO.
24
8
RSVD
23
7
22
6
21
5
20
4
19
3
DMAERR
18
2
TXDMAE
17
1
DS785UM1
RXDMAE
16
0
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