EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 316
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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9
9-14
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
of buffers as they are exchanged with the MAC. When the MAC reads a descriptor, it keeps a
copy of the index, which it includes in any status entry associated with that buffer. The Not
Start Of Frame bit may be set by the Host on any buffer in which it does not want a new frame
to be started. This buffer would then only be used for chaining of frame fragments. This mode
may be used to align frames on boundaries coarser than descriptors, such as when multiple
physical address descriptors are used to describe one virtual address buffer.
In normal operation, the Host does not need to access the RXDQBAdd, RXDQBLen,
RXDCurAdd registers following initialization. Control of the use of the descriptors is handled
using the Receive Descriptor Enqueue register (RXDEnq). The term enqueue refers to the
action of adding descriptors to the end of an existing queue. To enqueue receive descriptors,
the Host writes the number of descriptors to the RXDEnq register. The number is
automatically added to the existing value. When the MAC consumes descriptors by reading
them into its on local storage (internal MAC buffer), the number read is subtracted from the
total. The Host can read the total number of unread valid descriptors left in the queue from
the RXDEnq. There is a restriction that no more than 255 descriptors may be added to the
queue in one write operation. To add more than this number requires multiple write
operations. See
Receive Descriptor queue
Base Length (RxDBL)
Receive Descriptor
queue Base Address
RxDBA (32)
Figure
Figure 9-7. Receive Descriptor Format and Data Fragments
9-7.
Not
SOF
(1)
Not
SOF
(1)
Not
SOF
(1)
Not
SOF
(1)
Indx 0 (15)
Indx 1 (15)
Receive Descriptor Format
Indx 2 (15)
Indx k (15)
Buffer
Buffer
Buffer
Buffer
and Data Fragments
Copyright 2007 Cirrus Logic
RxBufAdr 0 (32)
RxBufAdr 1 (32)
RxBufAdr 2 (32)
RxBufAdr k (32)
Buffer length
0 to 64 Kbytes
in multiples of 4-bytes
Length k (16)
Length 2 (16)
Length 1 (16)
Length 0 (16)
Buffer
Buffer
Buffer
Buffer
Each Data Buffer
begins and ends
on a 4-byte boundary.
register sizes are in bits,
and shown in parentheses ().
Data Buffer 0
Data Buffer 1
Data Buffer 2
Data Buffer k
Buffer 0
in bytes
Buffer 1
in bytes
Buffer 2
in bytes
Length
Length
Length
Buffer k
in bytes
Length
DS785UM1
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