EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 595
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
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Part Number
Manufacturer
Quantity
Price
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DS785UM1
Note: This bit reflects the status associated with the last character read from the RX FIFO. It
Note: This bit reflects the status associated with the last character read from the RX FIFO. It
changes with reads from the RX FIFO.
changes with reads from the RX FIFO.
RAB:
RTO:
EOF:
RFL:
RIL:
RFC:
RFS:
Copyright 2007 Cirrus Logic
Receiver Abort. (Read Only)
0 - No abort has been detected for the incoming frame.
1 - Abort detected during receipt of incoming frame. The
most recently read data is the last valid data before the
abort. EOF is also set.
Receiver Time Out.
Set to “1” whenever the HDLC RX has received four
consecutive flags, or four character times of idle or space.
Cleared by writing a “1” to this bit.
End of Frame (read only).
0 - Current frame has not been received completely.
1 - The data most recently read from the RX FIFO is the
last byte of data within the frame.
Receive Frame Lost. (Read/Write)
Set to “1” when an ROR occurred at the start of a new
frame, before any data for the frame could be put into the
RX FIFO. Cleared by writing a “1” to this bit.
Receive Information buffer Lost. (Read/Write)
Set to “1” when the last data for a frame is read from the
RX FIFO and the UART1HDLCRXInfoBuf has not been
read since the last data of the previous frame was read.
That is, the information loaded into the
UART1HDLCRXInfoBuf about the previous frame was
never read and has been overwritten. Cleared by writing a
“1” to this bit.
Received Frame Complete. (Read/Write)
Set to “1” when the last data byte for the frame is read
from the RX FIFO (this also triggers an update of the
UART1HDLCRXInfoBuf). Cleared by writing to a “1” to this
bit.
Receive FIFO Service request. (Read Only)
This bit is a copy of the RIS bit in the UART interrupt
identification register.
0 - RX FIFO is empty or RX is disabled.
1 - RX FIFO not empty and RX enabled.
May generate an interrupt and signal a DMA service
request.
UART3 With HDLC Encoder
EP93xx User’s Guide
16-19
16
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