EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 785
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
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Part Number
Manufacturer
Quantity
Price
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- Download datasheet (13Mb)
IDEMDMADataIn
IDEUDMADataOut
DS785UM1
31
15
31
15
Bit Descriptions:
Address:
Default:
Definition:
Bit Descriptions:
Address:
Default:
Definition:
30
14
30
14
29
13
29
13
28
12
28
12
DMA controller. A write by the host during MDMA data-out operation will
erroneously interfere with the MDMA state machine. Any read will return zero.
IDEDD:
0x800A_001C - Read Only (should be read by the DMA controller only)
0x0000_0000
In MDMA data-in operations, this register contains the data in the input buffer
just transferred from the device. The data is read from this register by the DMA
controller. This register should only be addressed and read by the DMA
controller. A read by the host during MDMA data-in operation will erroneously
interfere with the MDMA state machine. Any write is ignored.
IDEDD:
0x800A_0020 - Write Only (should be written by the DMA controller only)
0x0000_0000
In UDMA data-out operations, this register contains the data at the tail of the
output buffer to be written by the DMA controller. This register should only be
27
11
27
11
26
10
26
10
Copyright 2007 Cirrus Logic
25
25
9
9
IDE output data in the output buffer in MDMA mode.
IDE input data in the input buffer in MDMA mode.
24
24
8
8
IDEDD
IDEDD
IDEDD
IDEDD
23
23
7
7
22
22
6
6
21
21
5
5
20
20
4
4
19
19
3
3
EP93xx User’s Guide
18
18
2
2
IDE Interface
17
17
1
1
27-15
16
16
0
0
27
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