LFE3-95E-PCIE-DKN Lattice, LFE3-95E-PCIE-DKN Datasheet - Page 100

• Manufacturer Part Number: LFE3-95E-PCIE-DKN
• Description: MCU, MPU & DSP Development Tools LatticeECP3 PCI Express Dev Kit
• Manufacturer: Lattice

Specifications of LFE3-95E-PCIE-DKN

• Processor To Be Evaluated: LFE3-95EA-x
• Processor Series: LatticeECP3
• Interface Type: SPI
• Operating Supply Voltage: 1.2 V to 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LatticeECP3 sysCONFIG Port Timing Specifications
POR, Configuration Initialization, and Wakeup
t
t
t
t
t
t
t
t
t
All Configuration Modes
t
t
t
Slave Serial
t
t
f
Master and Slave Parallel
t
t
t
t
t
t
t
t
t
f
Master and Slave SPI
t
t
t
t
f
t
t
t
Parameter
ICFG
VMC
PRGM
PRGMRJ
DPPINIT
DPPDONE
DINIT
MWC
CZ
SUCDI
HCDI
CODO
SSCH
SSCL
CCLK
SUCS
HCS
SUWD
HWD
DCB
CORD
BSCH
BSCL
BSCYC
CCLK
CFGX
CSSPI
SOCDO
CSPID
CCLK
SSCH
SSCL
HLCH
Time from the Application of V
is the Last to Cross the POR Trip Point) to the Rising Edge of
INITN
Time from t
PROGRAMN Low Time to Start Configuration
PROGRAMN Pin Pulse Rejection
Delay Time from PROGRAMN Low to INITN Low
Delay Time from PROGRAMN Low to DONE Low
PROGRAMN High to INITN High Delay
Additional Wake Master Clock Signals After DONE Pin is High
MCLK From Active To Low To High-Z
Data Setup Time to CCLK/MCLK
Data Hold Time to CCLK/MCLK
CCLK/MCLK to DOUT in Flowthrough Mode
CCLK Minimum High Pulse
CCLK Minimum Low Pulse
CCLK Frequency
CSN[1:0] Setup Time to CCLK/MCLK
CSN[1:0] Hold Time to CCLK/MCLK
WRITEN Setup Time to CCLK/MCLK
WRITEN Hold Time to CCLK/MCLK
CCLK/MCLK to BUSY Delay Time
CCLK to Out for Read Data
CCLK Minimum High Pulse
CCLK Minimum Low Pulse
Byte Slave Cycle Time
CCLK/MCLK Frequency
INITN High to MCLK Low
INITN High to CSSPIN Low
MCLK Low to Output Valid
CSSPIN[0:1] Low to First MCLK Edge Setup Time
CCLK Frequency
CCLK Minimum High Pulse
CCLK Minimum Low Pulse
HOLDN Low Setup Time (Relative to CCLK)
ICFG
to the Valid Master MCLK
Over Recommended Operating Conditions
CC
, V
CCAUX
Description
or V
CCIO8
3-48
* (Whichever
DC and Switching Characteristics
Master mode
Slave mode
Without encryption
With encryption
Without encryption
With encryption
Without encryption
With encryption
LatticeECP3 Family Data Sheet
Min.
100
0.2
0.3
25
30
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
1
5
5
7
1
7
1
6
6
5
5
5
Max.
500
300
23
10
37
37
12
33
20
12
12
33
20
80
15
33
20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6
1
2
5
cycles
Units
MHz
MHz
MHz
MHz
MHz
MHz
ms
ms
ms
ns
ns
ns
ns
µs
µs
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns