LFE3-95E-PCIE-DKN Lattice, LFE3-95E-PCIE-DKN Datasheet - Page 102
LFE3-95E-PCIE-DKN
Manufacturer Part Number
LFE3-95E-PCIE-DKN
Description
MCU, MPU & DSP Development Tools LatticeECP3 PCI Express Dev Kit
Manufacturer
Lattice
Datasheet
1.LFE3-150EA-7FN672CTW.pdf
(130 pages)
Specifications of LFE3-95E-PCIE-DKN
Processor To Be Evaluated
LFE3-95EA-x
Processor Series
LatticeECP3
Interface Type
SPI
Operating Supply Voltage
1.2 V to 3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Lattice Semiconductor
Figure 3-17. sysCONFIG Parallel Port Write Cycle
Figure 3-18. sysCONFIG Master Serial Port Timing
Figure 3-19. sysCONFIG Slave Serial Port Timing
WRITEN
1. In Master Parallel Mode the FPGA provides CCLK (MCLK). In Slave Parallel Mode the external device provides CCLK.
CCLK (output)
CCLK (input)
CCLK
CS1N
BUSY
D[0:7]
CSN
DOUT
1
DOUT
DIN
DIN
t
SUCBDI
t
t
SUWD
SUCS
Byte 0
t
t
SUSCDI
SUMCDI
t
BSCL
Byte 1
t
HCBDI
3-50
t
SSCL
Byte 2
t
DCB
t
BSCYC
t
BSCH
DC and Switching Characteristics
t
t
CODO
CODO
LatticeECP3 Family Data Sheet
t
SSCH
Byte n
t
t
HSCDI
HMCDI
t
HCS
t
HWD
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