DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 13

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

2.10 Line Interface
2.11 MAC Interface
2.12 Clock Synthesizer
2.13 Jitter Attenuator
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Requires a single master clock (MCLK) for both E1 and T1 operation. Master clock can be 2.048MHz,
4.096MHz, 8.192MHz, or 16.384MHz. Option to use 1.544MHz, 3.088MHz, 6.276MHz, or 12.552MHz
for T1-only operation
Fully software configurable
Short- and long-haul applications
Automatic receive sensitivity adjustments
Ranges include 0dB to -43dB or 0dB to -12dB for E1 applications; 0dB to -36dB or 0dB to -15dB for T1
applications
Receive level indication in 2.5dB steps from -42.5dB to -2.5dB
Internal receive termination option for 75Ω, 100Ω, and 120Ω lines
Monitor application gain settings of 20dB, 26dB, and 32dB
G.703 receive-synchronization signal-mode
Flexible transmit-waveform generation
T1 DSX-1 line build-outs
T1 CSU line build-outs of -7.5dB, -15dB, and -22.5dB
E1 waveforms include G.703 waveshapes for both 75Ω coax and 120Ω twisted cables
AIS generation independent of loopbacks
Alternating ones and zeros generation
Square-wave output
Open-drain output option
NRZ format option
Transmitter power-down
Transmitter 50mA short-circuit limiter with exceeded indication of current limit
Transmit open-circuit-detected indication
Line interface function can be completely decoupled from the framer/formatter
MAC port with standard MII (less TX_ER) or RMII
10Mbps and 100Mbps data rates
Configurable DTE or DCE modes
Facilitates auto-negotiation by host microprocessor
Programmable half- and full-duplex modes
Flow control for both half-duplex (back-pressure) and full-duplex (PAUSE) modes
Programmable Maximum MAC frame size up to 2016 bytes
Minimum MAC frame size: 64 bytes
Discards frames greater than programmed maximum MAC frame size and runt, nonoctet bounded, or
bad-FCS frames upon reception
Programmable threshold for SDRAM queues to initiate flow control and status indication
MAC loopback support for transmit data looped to receive data at the MII/RMII interface
Output frequencies include 2.048MHz, 4.096MHz, 8.192MHz, and 16.384MHz
Derived from recovered line clock or master clock
32-bit or 128-bit crystal-less jitter attenuator
Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use 1.544MHz
for T1 operation
Can be placed in either the receive or transmit path or disabled
Limit trip indication
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