DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 327

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

15 JTAG INFORMATION
This device contains dual JTAG controllers and requires special consideration during JTAG test design. For more
information on performing JTAG testing using this device, go to www.maxim-ic.com/support.
The device supports the standard instruction codes SAMPLE:PRELOAD, BYPASS, and EXTEST. Optional public
instructions included are HIGHZ, CLAMP, and IDCODE. See
required by IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture.
The Test Access Port has the necessary interface pins: JTRSTn, JTCLKn, JTMSn, JTDIn, and JTDOn. See the pin
descriptions for details. Refer to IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994 for details about
the Boundary Scan Architecture and the Test Access Port.
Figure 15-1. JTAG Functional Block Diagram
Test Access Port (TAP)
TAP Controller
Instruction Register
DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
10K
JTDI
10K
JTMS
Bypass
Register
Register
Register
Register
Controller
Instruction
Identification
Boundary Scan
Test Access Port
JTCLK
10K
JTRST*
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Select
Tri-State
Mux
Table
JTDO
Bypass Register
Boundary Scan Register
Device Identification Register
15-1. The device contains the following as